Patent EP0600434A2 successfully refreshed from Google Patents.
EP0600434A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Semiconductor memory device
Assignee: Panasonic Holdings Corp
•
Filing: 1993-11-30
•
Granted: —
•
Expires: 2013-11-30
Abstract
Abstract Bit lines BL0 and /BL0 are connected to a sense amplifier SA0, the gate of a first MOS transistor to a first word line WL0, a first electrode of a first ferrodielectric capacitor Cs1 to the source of the first Qn, the drain of the first Qn to BL0, a second electrode of Cs1 to a first plate electrode CP0, the gate of a second MOS transistor Qn to a second word line DWL0, a first electrode of a second ferrodielectric capacitor Cd2 to the source of the second Qn, the drain of the second Qn to /BL0, and a second electrode of Cd1 to a second plate electrode DCP0, and after turning off the second Qn, the logic voltage of DCP0 is inverted. Hence, in a semiconductor memory device employing the ferrodielectric element, the dummy memory capacitor is initialized securely, and high speed reading is enabled without concentration of power consumption.
Inventors
- 👤 Hiroshige Hirano
- 👤 Tatsumi Sumi
- 👤 Nobuyuki Moriwaki
- 👤 George Nakane
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-06 13:30
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/22; G11C5/00; G11C5/06; G11C5/063
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
160 words
A semiconductor memory device comprising: an amplifier, a first bit line and a second bit line being connected to this amplifier, a first ferrodielectric capacitor, a first MOS transistor, in this first MOS transistor, a first word line is connected to its gate, a first electrode of the first ferrodielectric capacitor is connected to the source, and the first bit line is connected to the drain, a second electrode of the first ferrodielectric capacitor being connected to a first plate electrode, a second ferrodielectric capacitor, and a second MOS transistor, in this second MOS transistor, a second word line is connected to is gate, a first electrode of the second ferrodielectric capacitor is connected to the source, and the second bit line is connected to the drain, a second electrode of the second ferrodielectric capacitor being connected to a second plate electrode, wherein the logic voltage of the second plate electrode is inverted after turning off the second MOS transistor.
Claim 2
Dependent Claim
38 words
A semiconductor memory device of claim 1, wherein the logic voltage of the first plate electrode and second plate electrode is inverted after turning off the second MOS transistor, and then the first MOS transistor is turned off.
Claim 3
Dependent Claim
18 words
A semiconductor memory device of claim 2, wherein the first plate electrode and second plate electrode are connected.
Claim 4
Dependent Claim
64 words
A semiconductor memory device of claim 1, wherein before start or after end of writing or reading action of memory cell data, the second bit line is set at a certain logic voltage, turn on the second MOS transistor, and then the logic voltage of the second plate electrode is set to a reverse value of the logic voltage of the second bit line.
Claim 5
Dependent Claim
185 words
A semiconductor memory device comprising: an amplifier, a first bit line and a second bit line being connected to this amplifier, a first ferrodielectric capacitor, a first MOS transistor, in this first MOS transistor, a first word line is connected to its gate, a first electrode of the first ferrodielectric capacitor is connected to the source, and the first bit line is connected to the drain, a second electrode of the first ferrodielectric capacitor being connected to a first plate electrode, a second ferrodielectric capacitor, a second MOS transistor, in this second MOS transistor, a second word line is connected to is gate, a first electrode of the second ferrodielectric capacitor is connected to the source, and the second bit line is connected to the drain, a second electrode of the second ferrodielectric capacitor being connected to a second plate electrode, and a third MOS transistor, in this third MOS transistor, an initializing control signal line is connected to its gate, an initializing potential signal line is connected to the source, and the first electrode of the second ferrodielectric capacitor is connected to the drain.
Claim 6
Dependent Claim
18 words
A semiconductor memory device of claim 5, wherein the first plate electrode and second plate electrode are connected.
Claim 7
Dependent Claim
20 words
A semiconductor memory device of claim 5, wherein the data initializing potential signal line is connected to the grounding potential.
Claim 8
Dependent Claim
41 words
A semiconductor memory device of claim 5, wherein the logic voltage of the first bit line and the logic voltage of the second bit line are both grounding potential, before start of writing or reading action of the memory cell data.
Claim 9
Dependent Claim
45 words
A semiconductor memory device of claim 5, wherein after turning off the second MOS transistor, the third MOS transistor is turned on, and the logic voltages of the first plate electrode and second plate electrode are inverted, then the first MOS transistor is turned off.
Claim 10
Dependent Claim
40 words
A semiconductor memory device of claim 1, wherein the logic voltage of the first plate electrode before start of reading action of the memory cell data is an inverse logic voltage of the logic voltage of the first bit line.
Claim 11
Dependent Claim
40 words
A semiconductor memory device of claim 5, wherein the logic voltage of the first plate electrode before start of reading action of the memory cell data is an inverse logic voltage of the logic voltage of the first bit line.
Claim 12
Dependent Claim
52 words
A semiconductor memory device of claim 1, wherein the logic voltage of the second plate electrode and the logic voltage of the first electrode of the second ferrodielectric capacitor before start of reading action of the memory cell data are reverse logic voltages of the logic voltage of the second bit line.
Claim 13
Dependent Claim
52 words
A semiconductor memory device of claim 5, wherein the logic voltage of the second plate electrode and the logic voltage of the first electrode of the second ferrodielectric capacitor before start of reading action of the memory cell data are reverse logic voltages of the logic voltage of the second bit line.
Claim 14
Dependent Claim
52 words
A semiconductor memory device of claim 1, wherein the logic voltage of the second plate electrode and the logic voltage of the second bit line before start of reading action of the memory cell data are inverse logic voltages of the logic voltage of the first electrode of the second ferrodielectric capacitor.
Claim 15
Dependent Claim
52 words
A semiconductor memory device of claim 5, wherein the logic voltage of the second plate electrode and the logic voltage of the second bit line before start of reading action of the memory cell data are inverse logic voltages of the logic voltage of the first electrode of the second ferrodielectric capacitor.
Claim 16
Dependent Claim
34 words
A semiconductor memory device of claim 10, wherein at least one of the logic voltage of the first plate electrode and the logic voltage of the second plate electrode is always the same value.
Claim 17
Dependent Claim
34 words
A semiconductor memory device of claim 11, wherein at least one of the logic voltage of the first plate electrode and the logic voltage of the second plate electrode is always the same value.
Claim 18
Dependent Claim
34 words
A semiconductor memory device of claim 12, wherein at least one of the logic voltage of the first plate electrode and the logic voltage of the second plate electrode is always the same value.
Claim 19
Dependent Claim
33 words
A semiconductor memory device of claim 1, wherein after turning on the first MOS transistor and second MOS transistor, the logic voltages of the first plate electrode and second plate electrode are inverted.
Claim 20
Dependent Claim
33 words
A semiconductor memory device of claim 5, wherein after turning on the first MOS transistor and second MOS transistor, the logic voltages of the first plate electrode and second plate electrode are inverted.
Claim 21
Dependent Claim
64 words
A semiconductor memory device of claim 1, wherein after turning on the first MOS transistor and second MOS transistor, precharging of the first bit line and second bit line into one logic voltage is terminated before start of reading action or writing action of the memory cell data, and then the logic voltages of the first plate electrode and second plate electrode are inverted.
Claim 22
Dependent Claim
64 words
A semiconductor memory device of claim 5, wherein after turning on the first MOS transistor and second MOS transistor, precharging of the first bit line and second bit line into one logic voltage is terminated before start of reading action or writing action of the memory cell data, and then the logic voltages of the first plate electrode and second plate electrode are inverted.
Claim 23
Dependent Claim
33 words
A semiconductor memory device of claim 1, wherein after inverting the logic voltages of the first plate electrode and second plate electrode, the first MOS transistor and second MOS transistor are turned on.
Claim 24
Dependent Claim
33 words
A semiconductor memory device of claim 5, wherein after inverting the logic voltages of the first plate electrode and second plate electrode, the first MOS transistor and second MOS transistor are turned on.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.