Patent EP0597706A2 successfully refreshed from Google Patents.
EP0597706A2
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EP
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Solid state peripheral storage device
Assignee: Silicon Storage Technology Inc
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Filing: 1993-11-11
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Granted: —
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Expires: 2013-11-11
Abstract
Abstract A solid state peripheral storage device (10) receives an LSN (logical sector number) address from a computer system (12) and provides a mapping (74) to PSN (physical sector number) data. The PSN data is used to address memory units (80) made out of solid state floating gate storage cells. A microsequencer (50) controls the operation of the translation of the mapping (74) of the LSN to PSN and the accessing of the memory units (80). Through the use of the mapping of LSN to PSN, defective sectors in the memory units (80) can be mapped out and fresh, unused, defect-free sectors can then be replaced, all automatically, without user intervention. The microsequencer (50) has error recovery routines to further enhance the reliability of the peripheral device (10). Data to be written into the memory units (80) is initially transferred from the computer system (12) to a data register (35). The LSN address is stored in an LSN register (36). The data register (35) also serves as an output buffer store in a read operation.
Inventors
- 👤 Juei-Chi Hsu
- 👤 Ping Wang
- 👤 Ching S. Jenq
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-26 17:46
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/70; G11C29/76; G11C29/765; G11C29/88; G06; G06F; G06F11/00; G06F11/07; G06F11/08; G06F11/10; G06F11/1008; G06F11/1068; G11C29/74
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
114 words
A solid state storage apparatus for interfacing with a computer providing a first address signal, said apparatus comprising: means for translating said first address signal into a second address signal; memory means for storing data signals, said memory means comprising a plurality of floating gate storage cells; means for addressing said memory means with said second address signal to supply data signals thereto from said computer for storage or to retrieve data signals therefrom supplied to said computer; and means for changing said means for translating said first address signal to a third address signal in the event said floating gate storage cells in said memory means at said second address signal are defective.
Claim 2
Dependent Claim
45 words
The apparatus of Claim 1 wherein said addressing means further comprises: means for reading the data signals from said memory means in two modes: wherein in a first mode each of said addressed floating gate storage cells is sensed longer than in the second mode.
Claim 3
Dependent Claim
59 words
The apparatus of Claim 1 wherein said memory means for storing a first and a second data signals with said first data signals stored in a first plurality of floating gate storage cells at said second address signal, and said second data signals, representing said first address signal, stored redundantly in a second plurality of floating gate storage cells.
Claim 4
Dependent Claim
90 words
A solid state peripheral storage device for interfacing with a computer providing a logical sector signal, said device comprising: means for translating said logical sector signal into a physical sector signal; memory means for storing data signals, said memory means comprising a plurality of floating gate storage cells, and means for addressing said memory means with said physical sector signal for reading the data signals therefrom in two modes: wherein in a first mode each of said addressed floating gate storage cells is sensed longer than in the second mode.
Claim 5
Dependent Claim
43 words
The device of Claim 4 further comprising: means for changing said means for translating said logical sector signal into a new physical sector signal in the event said floating gate storage cells in said memory means at said physical sector signal are deflective.
Claim 6
Dependent Claim
59 words
The device of Claim 5 wherein said memory means for storing a first and a second data signals with said first data signals stored in a first plurality of floating gate storage cells at said physical sector signal, and said second data signals, representing said logical sector signal, stored redundantly in a second plurality of floating gate storage cells.
Claim 7
Dependent Claim
94 words
A solid state peripheral storage device for interfacing with a computer providing a logical sector signal, said device comprising: means for translating said logical sector signal into a physical sector signal; and memory means for storing a first and a second data signals, said memory means comprising a plurality of floating gate storage cells; said first data signals stored in a first plurality of floating gate storage cells at said physical sector signal, and said second data signals, representing said logical sector signal, stored redundantly in a second plurality of floating gate storage cells.
Claim 8
Independent Claim
160 words
A method of writing data signals from a computer to a solid state peripheral storage device comprising: supplying a logical sector signal and said data signals from said computer to said device; converting said logical sector signal into a physical sector address signal based upon a conversion table; writing said data signals into a memory means comprising a plurality of floating gate storage cells at said physical sector address signal; reading said data signals from said memory means from said physical sector address signal; comparing said data signals written into said memory means with said data signals read from said memory means; and in the event of an error: locating a new physical sector address signal addressing an unused portion of said memory means; writing said data signals into said memory means at said new physical sector address signal; and updating said conversion table to reflect the correspondence between the logical sector signal with said new physical sector address signal.
Claim 9
Independent Claim
145 words
A method of reading data signals from a solid state peripheral storage device supplied to a computer, comprising: supplying a logical sector signal from said computer to said device; converting said logical sector signal into a physical sector address signal based upon a conversion table; reading said data signals from a memory means comprising a plurality of floating gate storage cells at said physical sector address signal; determining if said data signals is correct by applying an error correction method; and in the event of a correctable error: locating a new physical sector address signal addressing an unused portion of said memory means; writing said data signals corrected by said error correction method into said memory means at said new physical sector address signal; and updating said conversion table to reflect the correspondence between the logical sector signal with said new physical sector address signal.
Claim 10
Dependent Claim
217 words
A solid state peripheral storage device for interfacing with a computer providing a command signal, a first address signal and a data signal; said device comprising: first register means for storing said command signal and said first address signal; second register means for storing said data signal; first memory means for storing a table of conversion of said first address signal into a second address signal, said first memory means comprising a plurality of floating gate storage cells; a dual port memory means having two ports, a first port and a second port with said first port in communication with said second register means; second memory means for storing said data signal, said second memory means comprising a plurality of floating gate storage cells; and sequencer means connected to said first register means for receiving said command signal and said first address signal, and connected to said first memory means for converting said first address signal into said second address signal; said sequencer having means for addressing said second memory means with said second address signal to store said data signals therein, or to retrieve stored data signal therefrom; said sequencer further having means for correcting said stored data signal and to provide said stored data signal to said second port of said dual port memory means.
Claim 11
Dependent Claim
21 words
The device of Claim 10 further comprising: controller means for storing a control program for interfacing said computer with said device.
Claim 12
Dependent Claim
21 words
The device of Claim 11, wherein said controller means further comprises third memory means for storing driver software for said device.
Claim 13
Dependent Claim
26 words
The device of Claim 12, wherein said controller means further comprises for switching access between said third memory means and said first and second register means.
Claim 14
Independent Claim
186 words
A method of formatting a solid state peripheral storage device for interfacing with a computer for receiving a logical sector signal therefrom, said device having a first memory means for translating said logical sector signal into a physical sector signal, and a second memory means having a plurality of physical sectors, each physical sector having a plurality of floating storage cells for the storage of data signals, said method comprising the steps of: storing charges on each of said plurality of floating gate storage cells in each of said physical sectors; subjecting each of said plurality of floating gate storage cells to a plurality of manufacturing screening tests; reading each of said plurality of floating gate storage cells in each of said physical sectors, and determining those sectors having storage cells which have failed to pass said plurality of manufacturing screening tests (hereinafter: "bad sectors"); marking an indicia in said bad sectors; reading said device to determine the sectors having the indicia marked; and storing the address of the sector with the indicia in the first memory means, as the physical sector signal to be excluded.
Claim 15
Dependent Claim
107 words
The method of Claim 14 further comprising the steps of: writing repeatedly different data patterns into said plurality of floating gate storage cells in sectors (hereinafter: "non-bad" sectors) whose address are not stored in the first memory means, as physical sector signals to be excluded; reading said data patterns from said plurality of floating gate storage cells of said non-bad sectors; comparing said data pattern written into said non-bad sectors with said data pattern read therefrom; and storing the address of the sector in the first memory means, whose data pattern written does not match the data pattern read as physical sector signals to be further excluded.
Claim 16
Dependent Claim
108 words
The method of Claim 14 further comprising the steps of: writing repeatedly different data patterns into said plurality of floating gate storage cells in sectors (hereinafter: "non-bad" sectors) whose address are not stored in the first memory means, as physical sector signals to be excluded; reading said data patterns from said plurality of floating gate storage cells of said non-bad sectors; comparing said data pattern written into said non-bad sectors with said data pattern read therefrom; and storing the address of the sector in the first memory means, whose data pattern written matches the data pattern read, as a physical sector signal mapped to a logical sector signal.
References Cited (Backward Citations)
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