Patent US6070256A successfully refreshed from Google Patents.
Patent EP0596657A2 successfully refreshed from Google Patents.
EP0596657A2
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EP
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Normalization of apparent propagation delay
Assignee: AT&T Inc
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Filing: 1993-10-28
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Granted: —
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Expires: 2013-10-28
Abstract
Abstract An integrated circuit includes a clock alignment circuit (10) having a frequency synthesizer (12) for receiving a reference clock signal (CLKIN) at a lower frequency and for generating phases (CLK1, CLK2, CLK3, CLK4) of an oscillator clock signal at a higher frequency. The oscillator clock signal phases (CLK1, CLK2, CLK3, CLK4) drive a desired clock signal phase generating circuit 26 that generates various phases of the desired clock signal. The desired clock signal phases (CLK1, CLK2, CLK3, CLK4) are systematically compared to the reference clock signal (CLKIN). The phase of the desired clock signal that is determined to align with the reference clock signal (CLKIN) is provided as the desired clock signal output from the integrated circuit such that there is no apparent time delay through the integrated circuit. In an alternate embodiment, a single phase of the desired clock signal is selected and a phase locked loop adjusts the oscillator (20) in the frequency synthesizer (12) to align the selected phase of the desired clock signal with the reference clock signal (CLKIN).
Inventors
- 👤 Richard Muscavage
- 👤 Robert Leonard Pritchett
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-08 14:59
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/04; G06F1/08; G06F1/10
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
75 words
An integrated circuit, comprising: a frequency synthesizer (12) for receiving a reference clock signal and for generating phases of an oscillator output clock signal (CLKIN); a desired clock signal phase generating circuit (26) for receiving the oscillator output clock signal phases and for generating various phases of a desired clock signal; and a clock phase selection circuit (28) for selecting one of the desired clock signal phases for comparison to the reference clock signal (CLKIN).
Claim 2
Dependent Claim
98 words
An integrated circuit as recited in claim 1, further comprising: a masking circuit (32) for defining a window of time during which alignment of the desired clock signal with the reference clock signal should occur; and a phase detector (34) for receiving the reference clock signal and the selected one of the desired clock signal phases and for comparing the selected one of the desired clock signal phases to the reference clock signal during the window of time to determine if the selected one of the desired clock signal phases is aligned with the reference clock signal (CLKIN).
Claim 3
Dependent Claim
33 words
An integrated circuit as recited in claim 1, further comprising a clock phase sequencing circuit (30) for selecting another one of the desired clock signal phases for comparison to the reference clock signal.
Claim 4
Dependent Claim
48 words
An integrated circuit as recited in claim 1, further comprising a clock phase sequencing circuit (30) for systematically selecting another one of the desired clock signal phases for comparison to the reference clock signal (CLKIN) until a timing signal is identified as aligning with the reference clock signal.
Claim 5
Dependent Claim
34 words
An integrated circuit as recited in claim 4, wherein the clock phase sequencing circuit (30) further comprises an accumulator for accumulating the number of desired clock signal phases compared to the reference clock signal.
Claim 6
Dependent Claim
23 words
An integrated circuit as recited in claim 2, further comprising an output pad (8) driven by the desired clock signal phase generating circuit.
Claim 7
Dependent Claim
101 words
An integrated circuit as recited in claim 1, wherein the desired clock signal phase generation circuit (26) comprises first and second desired clock signal phase generating circuits, and wherein the clock phase selection circuit comprises first and second clock phase selection circuits, the first clock phase selection circuiti (28) for selecting one of the phases generated by the first desired clock signal phase generating circuit as an output from the integrated circuit, and the second clock phase selection circuit for selecting one of the phases generated by the second desired clock signal phase generating circuit for feedback to the frequency synthesizer.
Claim 8
Dependent Claim
57 words
An integrated circuit as recited in claim 7, further comprising: an input driver (4) for receiving the reference clock signal and for providing the reference clock signal to the frequency synthesizer; a driver (120) for receiving the selected one of the phases generated by the second desired clock signal generating circuit for feedback to the frequency synthesizer.
Claim 9
Independent Claim
88 words
A method of aligning an oscillator generated clock output signal with a reference clock signal, comprising the steps of: generating multiple phases (CLK1, CLK2, CLK3, CLK4) of an oscillator output clock signal from a reference clock signal (CLKIN); employing the oscillator output clock phases (CLK1, CLK2, CLK3, CLK4) to generate a plurality of desired clock signal phases; and comparing one of the desired clock signal phases to the reference clock signal (CLKIN) to determine whether the compared desired clock signal phase is aligned with the reference clock signal.
Claim 10
Dependent Claim
44 words
A method as recited in claim 9, further comprising the step of defining a window of time (t w ) during which alignment of the desired clock signal with the reference clock signal should occur, and conducting the comparison during the window of time.
Claim 11
Dependent Claim
28 words
A method as recited in claim 9, further comprising the step of selecting another one of the desired clock signal phases for comparison to the reference clock signal.
Claim 12
Dependent Claim
27 words
A method as recited in claim 11, wherein the step of selecting a another one of the desired clock signal phases is accomplished by incrementing a counter.
Claim 13
Dependent Claim
45 words
A method as recited in claim 9, further comprising the step of selecting systematically another one of said desired clock signal phases for comparison to the reference clock signal (CLKIN) until a desired clock signal phase is identified that aligns with the reference clock signal.
Claim 14
Dependent Claim
29 words
A method as recited in claim 13, further comprising the step of providing the desired clock signal phase that aligns with the reference clock signal as an output signal.
Claim 15
Dependent Claim
24 words
A method as recited in claim 13, further comprising the step of accumulating the number of desired clock signal phases compared in an accumulator.
Claim 16
Independent Claim
249 words
A method of aligning two clock signals (DCF1 and DCF2) to each other, comprising the steps of: generating multiple phases of a first oscillator output clock signal from a reference clock signal (CLKIN); employing the phases of the first oscillator output clock signal to generate a plurality of first desired clock signal phases; systematically comparing the first desired clock signal phases to the reference clock signa (CLKIN), one at a time, until a first desired clock signal phase is identified as aligning with the reference clock signal; providing the phase of the first desired clock signal that is aligned with the reference clock signal as a first clock signal output, thereby aligning the first desired clock signal with the reference clock signal; generating multiple phases of a second oscillator output clock signal from a reference clock signal (CLKIN); employing the phases of the second oscillator output clock signal to generate a plurality of second desired clock signal phases; systematically comparing the second desired clock signal phases to the reference clock signal, one at a time, until a second desired clock signal phase is identified as aligning with the reference clock signal (CLKIN); providing the phase of the second desired clock signal that is aligned with the reference clock signal as a second clock signal output, thereby aligning the second desired clock signal with the reference clock signal, whereby the first and second clock signals are each aligned with the reference clock signal and therefore are aligned with each other.
Claim 17
Dependent Claim
25 words
A method as recited in claim 16, wherein the frequency of the first clock signal output differs from the frequency of the reference clock signal.
Claim 18
Dependent Claim
29 words
A method as recited in claim 16, further comprising the step of providing a synchronizing signal (154 or 154') between first and second clocks generating the two clock signals.
Claim 19
Dependent Claim
31 words
A method as recited in claim 18, wherein providing a synchronizing signal further comprises providing the first desired clock signal phase (154') as the reference clock signal to the second clock.
Claim 20
Dependent Claim
28 words
A method as recited in claim 18, wherein providing a synchronizing signal further comprises synchronizing a counter in the first clock with a counter in the second clock.
References Cited (Backward Citations)
No citation records indexed.
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