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EP0596636A2
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Cache tag memory
Assignee: STMicroelectronics lnc USA
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Filing: 1993-10-26
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Granted: —
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Expires: 2013-10-26
Abstract
Abstract A cache tag memory device having a memory array comprising a first single-port memory array, a second single-port memory array, and a dual-port memory array. A first port, accessed by a local processor, may read from and write to its corresponding single-port memory array and the dual-port memory array. A second port, accessed through a global system bus, may also read from and write to its corresponding second single-port memory array and the dual-port memory array Both ports operate asynchronously relative to each other. Status bits indicating the status of the entries in the first and second single-port memory arrays are stored in the dual-port memory array and may be altered by the global system while the local processor is performing its operations. <IMAGE>
Inventors
- 👤 David Charles Mcclure
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-27 11:07
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0806; G06F12/0815; G06F12/0831; G06F12/0844; G06F12/0853
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
206 words
A cache tag memory, comprising: a first-single port memory array having a plurality of entries; a dual-port memory array having a plurality of entries corresponding to the plurality of entries in the first single-port memory array; a second-single port memory array having a plurality of entries corresponding to the plurality of entries in the dual-port memory array and the first single-port memory array; a first memory port capable of writing entries to said first single-port memory array and said dual-port memory array, and capable of reading entries from said first single-port memory array and said dual-port memory array; a second memory port capable of reading entries from said second single-port memory array and said dual-port memory array, and capable of writing entries to said dual-port memory array; a first comparator connected to said first port for comparing an array entry selected by a first portion of a local address with a second portion of the local address, and for generating a signal indicative of a match; and a second comparator connected to said second port for comparing an array entry selected by a first portion of a global address with a second portion of the global address, and for generating a signal indicative of a match.
Claim 2
Dependent Claim
23 words
The cache tag memory of Claim 1, wherein said first memory port is capable of writing entries into said second single-port memory array.
Claim 3
Dependent Claim
24 words
The cache tag memory array of Claim 1, wherein said second memory port is capable or writing entries into said second single-port memory array.
Claim 4
Dependent Claim
40 words
The cache tag memory of Claim 1, wherein a valid state composed of a bit or bits is stored in said dual-port memory array to indicate the validity of an entry stored in the first and second single-port memory arrays.
Claim 5
Dependent Claim
30 words
The cache tag memory of Claim 4, wherein said valid state corresponding to said entry is set to a first value when a new value is written to the entry.
Claim 6
Dependent Claim
73 words
The cache tag memory of Claim 5, further comprising: comparison logic for determining whether the value of the entry indexed by a first portion of a global system address is the same as a second portion of the global system address, thereby defining a match; and logic means for setting the first valid state corresponding to such indexed entry to a second value if a match occurs during a global system write operation.
Claim 7
Dependent Claim
36 words
The cache tag memory of Claim 6, further comprising logic means for setting the first valid state corresponding to such indexed entry to the second value if a match occurs during a global system read operation.
Claim 8
Dependent Claim
28 words
The cache tag memory of Claim 6, wherein said comparison logic comprises a logic gate combined logically with said valid state and the output of the first comparator.
Claim 9
Dependent Claim
28 words
The cache tag memory of Claim 6, wherein said comparison logic comprises a logic gate combined logically with said valid state and the output of the second comparator.
Claim 10
Dependent Claim
29 words
The cache tag memory of Claim 6, wherein said logic means comprises a logic gate combined logically with a snoop write signal and the output of the second comparator.
Claim 11
Dependent Claim
21 words
The cache tag memory of Claim 1, further comprising control circuitry for writing into the first and second single-port memory arrays.
Claim 12
Dependent Claim
22 words
The cache tag memory of Claim 1, wherein at least one bit position in the dual-port memory array comprises a parity bit.
Claim 13
Dependent Claim
126 words
A cache memory, comprising: at least one local processor; a cache tag memory including a first single-port memory array portion, a second single-port memory array portion, and a dual-port memory array portion; a data cache for storing a plurality of entries; a cache controller for controlling exchanges of data or control signals between the local processor and a system bus; means for generating a first match signal for indicating a memory location addressed by the local processor resides in the data cache; means for generating a valid signal for indicating a memory location addressed by the local processor is valid; and means for generating a second match signal for indicating a memory location addressed by the system bus matches an entry in the cache tag memory.
Claim 14
Dependent Claim
36 words
The cache memory of Claim 13, further comprising means for generating a control signal to be communicated to the cache tag memory from the system bus indicating a write operation is occurring on the system bus.
Claim 15
Dependent Claim
23 words
The cache memory of Claim 13, further comprising means for invalidating an entry in the cache tag if the entry is accessed globally.
Claim 16
Dependent Claim
44 words
The cache memory of Claim 13, wherein said means for generating the second match signal for indicating the memory location addressed by the system bus matches an entry in the cache tag memory occurs when a write operation is occurring on the system bus.
References Cited (Backward Citations)
No citation records indexed.
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