NMOS LDD PMOS HALO IC process for CMOS transistors

Claim 2

The IC fabrication process of claim 1 wherein the step of introducing a relatively low dose of N type dopant material comprises implanting an N- concentration of N type dopant material in the S and D regions of NMOS and PMOS transistors forming an N-LDD layer in the NMOS transistors and an N- halo layer in PMOS transistors using the polygate as an SAT mask and using dual angle implants at opposite angles from the vertical for reducing shadow effects of the SAT mask; and wherein the step of introducing a relatively high P+ concentration S and D regions in the PMOS transistor over the halo layer comprises implanting P type dopant material using dual angle implants at opposite angles from the vertical.

Claim 3

The IC fabrication process of claim 2 wherein the NWELL of PMOS transistors comprises a retrograde concentration NWELL having a relatively low N-- concentration of N type dopant material near the surface of the NWELL, wherein the N-LDD layer and halo layer PHLDD comprise a relatively low N- concentration of N type dopant material, and wherein the PMOS transistor S and D regions comprise relatively high P+ concentration of P type dopant material.

Claim 4

The IC fabrication process of claim 3 wherein the NWELL N type dopant material comprises phosphorus, wherein the N-LDD layer and halo layer PHLDD N type dopant material comprises phosphorus, wherein the NMOS transistor N+ S and D regions comprise an N type dopant material of arsenic, and wherein the PMOS transistor P+ S and D regions comprise a P type dopant material of boron.

Claim 5

The IC fabrication process of claim 4 wherein the N-- concentration of N type dopant material in the NWELL is in the concentration range of approximately 1-5 x 10¹⁶ ions/cm³; wherein the N- concentration of N type dopant material in the N-LDD layer and halo layer PHLDD is in the concentration range of approximately 1 x 10¹⁷ ions/cm³; wherein the N+ concentration of N type dopant material in the NMOS transistor S and D regions is in the concentration range of approximately 1 x 10²⁰ ions/cm², and wherein the P+ concentration of P type dopant material is in the concentration range of 1-6 X10¹⁹ ions/cm₃.

Claim 6

The IC fabrication process of claim 1 wherein the process is a BICMOS IC fabrication process having an emitter annealing step before the P+S/D definition mask, etch, and introduction sequence, and comprising the step of using the emitter annealing step for driving the N type halo layer PHLDD under the polygate and into the ends of the channel under the polygate between the S and D regions of the PMOS transistors for controlling the dimensions of the localized halo to be left by the P+S/D definition mask, etch, and introduction sequence.

Claim 7

The IC fabrication of claim 1 wherein the operating voltage threshold (V T ) of PMOS transistors is established primarily by three CMOS fabrication process steps comprising a process step of introducing N type dopant material into the NWELL, a V T adjust process step comprising a blanket implant of P type dopant material in the active areas of CMOS transistors, and a process step of introducing N type dopant material into the LDD layer and halo layer.

Claim 8

The IC fabrication process of claim 7 wherein the three process steps make substantially equal contributions to establishing the operating voltage threshold (V T ) of PMOS transistors.

Claim 9

An integrated circuit CMOS transistor structure having NMOS and PMOS transistors produced by the process of claim 1 and having concentration ranges of dopant material across the active area of the respective PMOS transistor substantially as shown in Fig. 7.

Claim 10

An IC fabrication process incorporating CMOS fabrication steps for preparing CMOS transistors in a substrate of semiconductor material including an NWELL definition mask, etch and N type dopant material introduction sequence providing a relatively low N-- concentration NWELL in the substrate for PMOS transistors, a PWELL definition mask, etch and P type dopant material introduction sequence providing a relatively low P- concentration PWELL in the substrate for NMOS transistors, growing an epitaxial silicon layer by epitaxial deposition across the substrate, growing an epitaxial oxide (EPIOX) layer across the epitaxial layer and depositing a nitride layer (SIN) by chemical vapor deposition (CVD) over the EPIOX layer, an active area definition mask, etch, and field oxide (FOX) grow sequence for defining and framing the active areas of CMOS transistors in FOX, an active strip mask, etch, voltage threshold (V T ) adjust and gate oxide (GOX) grow sequence for adjusting the threshold voltage of CMOS transistors and preparing the surface of the CMOS transistor active areas for receiving a CMOS transistor gate, depositing a layer of polysilicon across the IC followed by a polygate definition mask and etch sequence for forming a polygate POLY over the GOX of CMOS transistor active areas, said polygate defining a channel in respective NWELL's and PWELL's under the respective polygates between source (S) and drain (D) regions, and forming a seal oxide (SPOX) over the respective polygates, the improvement for hot electron protection of the GOX of NMOS transistors and for enhanced punch through protection between source and drain regions of PMOS transistors, without substantially increasing parasitic capacitance across active areas of CMOS transistors, comprising: introducing a relatively low dose of N type dopant material in S and D regions of CMOS transistors using the polygate as a self aligned transistor (SAT) mask, and forming a low doped N type LDD layer in the S and D regions of NMOS transistors and a low doped N type halo PHLDD layer in the S and D regions of PMOS transistors, said N type halo layer having a relatively higher concentration than the NWELL near the surface of PMOS transistors; a PMOS transistor P+S/D definition mask, etch and P type dopant material introduction sequence introducing relatively high P+ concentration S and D regions in the PMOS transistors over the halo layer, and adjusting the P+S/D introduction sequence for erasing the halo layer along the horizontal interface between the PMOS transistor S and D regions and underlying NWELL, but preserving the halo layer at inner sides of the S and D regions at the ends of the channel under the polygate of the PMOS transistors thereby leaving a localized halo of N type dopant material for added punch through protection between the S and D regions of PMOS transistors without increasing parasitic capacitance along the major portion of the horizontal active area interface between S and D regions and underlying NWELL of PMOS transistors; and an NMOS transistor N+S/D definition mask, etch and N type material introduction sequence introducing relatively high N+ concentration S and D regions in the NMOS transistors over the LDD layer, and adjusting the N+S/D introduction sequence for retaining a portion of the N type LDD layer along the horizontal interface between the NMOS transistor S and D regions and underlying PWELL for reducing parasitic capacitance between S and D regions and underlying PWELL of NMOS transistors, and also providing an N type LDD layer at the ends of the channel under the polygate of NMOS transistors for hot electron protection of GOX.

Claim 11

The IC fabrication process of claim 10 wherein the step of introducing a relatively low dose of N type dopant material to form the LDD layer and halo layer comprises implanting an N- concentration of N type dopant material in the S and D regions of NMOS and PMOS transistors forming an N-LDD layer in the NMOS transistors and an N- halo layer in the PMOS transistors using the polygate as an SAT mask and using dual angle implants at opposite angles from the vertical for reducing shadow effects of the SAT mask; and wherein the step of introducing a relatively high P+ concentration S and D regions in the PMOS transistor over the halo layer comprises implanting P type dopant material using dual angle implants at opposite angles from the vertical.

Claim 12

The IC fabrication process of claim 10 wherein the NWELL of PMOS transistors comprises a retrograde concentration NWELL having a relatively low N-- concentration of N type dopant material near the surface of the NWELL, wherein the N-LDD layer and halo layer PHLDD comprise a relatively low N- concentration of N type dopant material, and wherein the PMOS transistor S and D regions comprise relatively high P+ concentration of P type dopant material.

Claim 13

The IC fabrication process of claim 12 wherein the NWELL N type dopant material comprises phosphorus, wherein the N-LDD layer and halo layer PHLDD N type dopant material comprises phosphorus, wherein the NMOS transistor N+ S and D regions comprise an N type dopant material of arsenic, and wherein the PMOS transistor P+ S and D regions comprise a P type dopant material of boron.

Claim 14

The IC fabrication process of claim 13 wherein the N-- concentration of N type dopant material in the NWELL is in the concentration range of approximately 1-5 x 10¹⁶ ions/cm³; wherein the N- concentration of N type dopant material in the N-LDD layer and halo layer PHLDD is in the concentration range of approximately 1 x 10¹⁷ ions/cm³; wherein the N+ concentration of N type dopant material in the NMOS transistor S and D regions is in the concentration range of approximately 1 x 10²⁰ ions/cm², and wherein the P+ concentration of P type dopant material is in the concentration range of 1-6 X10¹⁹ ions/cm³.

Claim 15

The IC fabrication process of claim 10 wherein the process is a BICMOS IC fabrication process having an emitter annealing step before the P+S/D definition mask, etch, and introduction sequence, and comprising the step of using the emitter annealing step for driving the N type halo layer PHLDD under the polygate and into the ends of the channel under the polygate between the S and D regions of the PMOS transistors for controlling the dimensions of the localized halo to be left by the P+S/D definition mask, etch, and introduction sequence.

Claim 16

The IC fabrication process of claim 10 wherein the operating voltage threshold (V T ) of CMOS transistors is established primarily by three PMOS fabrication process steps comprising a process step of introducing N type dopant material into the NWELL, a V T adjust process step comprising a blanket implant of P type dopant material in the active areas of CMOS transistors, and a process step of introducing N type dopant material into the LDD layer and halo layer.

Claim 17

The IC fabrication process of claim 16 wherein the three process steps make substantially equal contributions to establishing the operating voltage threshold (V T ) of PMOS transistors.

Claim 18

An integrated circuit CMOS transistor structure having NMOS and PMOS transistors produced by the process of claim 10 and having concentration ranges of dopant material across the active area of the respective PMOS transistor substantially as shown in Fig. 7.

Claim 19

CMOS transistors in a substrate of semiconductor material, said CMOS transistors comprising NMOS transistors having a PWELL, spaced apart source (S) and drain (D) regions of N type dopant material in the PWELL, and a polysilicon gate (polygate) separated by a gate oxide (GOX) layer from the source and drain regions and PWELL, said polygate defining a channel in the PWELL under the polygate between the S and D regions, and PMOS transistors having an NWELL, spaced apart source (S) and drain (D) regions of P type dopant material formed in the NWELL, and a polygate separated from source and drain regions and NWELL by a gate oxide (GOX) layer, said polygate defining a channel in the NWELL under the polygate between the S and D regions, the improvement for hot electron protection for the GOX of NMOS transistors, for enhanced punch through protection between S and D regions for PMOS transistors, and for reducing parasitic capacitance across active areas of CMOS transistors comprising: a low doped N type LDD layer in the S and D regions of NMOS transistors forming a graded concentration profile between N+ S and D regions and P- PWELL; relatively high P+ concentration S and D regions in the NWELL of PMOS transistors; an N type halo at inner sides of the S and D regions at the ends of the channel under the gate of the PMOS transistors forming a localized halo PHLDD of N type dopant material for added punch through protection between the S and D regions of PMOS transistors without increasing parasitic capacitance along the major portion of the horizontal active area between S and D regions and underlying NWELL of PMOS transistors, said halo PHLDD having a concentration of N type carriers greater than the NWELL where the halo meets the NWELL and being substantially symmetrical along the inner sides of the S and D regions; and relatively high N+ concentration S and D regions in the NMOS transistors over the LDD layer, a portion of the LDD layer lying along the horizontal interface between the NMOS transistor S and D regions and underlying PWELL and providing the graded concentration profile for reducing parasitic capacitance between S and D regions and underlying PWELL of NMOS transistors, said N type LDD layer also being located at the ends of the channel under the polygate of NMOS transistors for providing hot electron protection for GOX.

Claim 20

The CMOS transistors of claim 19 wherein the NWELL of PMOS transistors comprises a retrograde concentration NWELL having a relatively low N-- concentration of N type dopant material near the surface of the NWELL, wherein the LDD layer and halo layer comprise a relatively low N- concentration of N type dopant material, and wherein the PMOS transistor S and D regions comprise relatively high P+ concentration of P type dopant material; said N-- concentration of N type dopant material in the NWELL being in the concentration range of approximately 1-5 x 10¹⁶ ions/cm³, said N- concentration of N type dopant material in the LDD layer and halo layer being in the concentration range of approximately 1 x 10¹⁷ ions/cm³, said N+ concentration of N type dopant material in the NMOS transistor S and D regions being in the concentration range of approximately 1 x 10²⁰ ions/cm², and said P+ concentration of P type dopant material in the PMOS transistor S and D regions being in the concentration range of 1-6 x10¹⁹ ions/cm₃.