Patent EP0593152A2 successfully refreshed from Google Patents.
EP0593152A2
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EP
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Random access memory design
Assignee: Sun Microsystems Inc
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Filing: 1993-07-30
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Granted: —
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Expires: 2013-07-30
Abstract
Abstract An improved approach for breaking the bit lines of a semiconductor memory device into small pieces, referred to herein as Embedded Access Trees (EATs), is introduced. Embedded Access Trees enjoy the principal advantage of the banked approach by dividing long bit lines into several smaller bit lines to decrease the effective load which a selected cell must drive. However, EATs avoid most of the limitations of the banked approach, e.g., increased size, power and complexity. In a preferred embodiment of the invention, EATs are embedded into the existing full array and do not require additional peripheral decoders, MUXes or complex and costly global routing. For a given processing technology, the present invention permits a full memory array to be subdivided into more subarrays than the banked approach, with corresponding performance improvements. <IMAGE>
Inventors
- 👤 Mark R. Santoro
- 👤 Gary W. Bewick
- 👤 Lee S. Tavrow
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-29 13:05
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/411; G11C7/00; G11C7/18; G11C11/413; G11C11/417
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
129 words
A semiconductor memory device having an array of memory cells organized in a plurality of subarrays and circuitry for accessing said array of memory cells, wherein said accessing circuitry comprises: a plurality of first bit lines, each associated with a column of memory cells of one of said subarrays; a plurality of second bit lines, each associated with a set of said first bit lines from a plurality of said subarrays; and a plurality of switch mechanisms for electrically connecting one of said first bit lines of said set with said associated second bit line during a memory cell access operation; whereby the load that must be driven during a memory cell access operation is less than the load of the total of said set of first bit lines.
Claim 2
Dependent Claim
20 words
The memory device as set forth in Claim 1, wherein said plurality of switch mechanisms are formed within said array.
Claim 3
Dependent Claim
21 words
The memory device as set forth in Claim 1, wherein said plurality of second bit lines are formed within said array.
Claim 4
Dependent Claim
41 words
The memory device as set forth in Claim 1, wherein said plurality of switch mechanisms comprises circuitry for amplifying the signal on a selected first bit line when said first bit line is electrically connected to said associated second bit line.
Claim 5
Dependent Claim
17 words
The memory device as set forth in Claim 4, wherein said amplifying circuitry comprises a bipolar transistor.
Claim 6
Dependent Claim
18 words
The memory device as set forth in Claim 4, wherein said amplifying circuitry comprises an MOS sense amplifier.
Claim 7
Dependent Claim
32 words
The memory device as set forth in Claim 3, wherein said plurality of second bit lines are positioned within said plurality of subarrays adjacent to said associated set of first bit lines.
Claim 8
Dependent Claim
54 words
The memory device as set forth in Claim 7, wherein said plurality of first and second bit lines are formed in conductive layers and wherein said plurality of second bit lines are formed in a conductive layer that is positioned above the conductive layer in which said plurality of first bit lines are formed.
Claim 9
Dependent Claim
37 words
The memory device as set forth in Claim 7, wherein said plurality of second bit lines are formed in the same conductive layer as the conductive layer in which said plurality of first bit lines are formed.
Claim 10
Dependent Claim
64 words
The memory device as set forth in Claim 1, wherein the plurality of said switch mechanisms associated with a particular set of first bit lines are electrically connected to form a logical OR relationship between their respective output signals, whereby the signal on one of said first bit lines controls the signal on said associated second bit line during a memory cell access operation.
Claim 11
Dependent Claim
59 words
The memory device as set forth in Claim 1, wherein the plurality of switch mechanisms associated with a particular set of first bit lines are electrically connected to the plurality of switch mechanisms associated with an adjacent set of first bit lines to form a multiplexor function, whereby fewer of said second bit lines are required in said array.
Claim 12
Dependent Claim
48 words
The memory device as set forth in Claim 11, wherein said accessing circuitry further comprises a plurality of local word lines to select a particular memory cell within a subarray and a plurality of global word lines to select a particular subarray from among said plurality of subarrays.
Claim 13
Dependent Claim
51 words
The memory device as set forth in Claim 1, wherein said accessing circuitry comprises reading circuitry and writing circuitry, and wherein said plurality of second bit lines includes a set of second bit lines associated with said reading circuitry and a set of second bit lines associated with said writing circuitry.
Claim 14
Dependent Claim
20 words
The memory device as set forth in Claim 1, wherein said memory device is a static random access memory device.
Claim 15
Dependent Claim
20 words
The memory device as set forth in Claim 1, wherein said memory device is a dynamic random access memory device.
Claim 16
Dependent Claim
23 words
The memory device as set forth in Claim 1, wherein said plurality of first bit lines comprises differential pairs of first bit lines.
Claim 17
Dependent Claim
23 words
The memory device as set forth in Claim 1, wherein said plurality of second bit lines comprises differential pairs of second bit lines.
Claim 18
Dependent Claim
46 words
The memory device as set forth in Claim 13, wherein said reading circuitry includes circuitry positioned along one side of the perimeter of said plurality of subarrays and said writing circuitry includes circuitry positioned along an orthogonal side of the perimeter of said plurality of subarrays.
Claim 19
Dependent Claim
58 words
The memory device as set forth in Claim 1, further comprising a plurality of third bit lines, each associated with a set of said second bit lines; and a second plurality of switch mechanisms for electrically connecting one of said second bit lines of said set with said associated third bit line during a memory cell access operation.
Claim 20
Dependent Claim
60 words
The memory device as set forth in Claim 1, wherein said accessing circuitry comprises: circuitry for determining in which of said subarrays a read operation is to next occur; and circuitry for initiating said read operation earlier if said determining circuitry determines that said next read operation is to occur in a different subarray than the just previous write operation.
Claim 21
Dependent Claim
18 words
The memory device as set forth in Claim 4, wherein said amplifying circuitry consumes no significant static power.
Claim 22
Independent Claim
133 words
A method of accessing data from a semiconductor memory device, said semiconductor memory device comprising an array of memory cells organized in a plurality of subarrays, each of said memory cells having a first bit line associated therewith which extends the height of the subarray of said memory cell, said method comprising the steps of: selecting a memory cell to be accessed; placing data from said selected memory cell on the first bit line associated therewith; activating a switch mechanism to transfer said data from said associated first bit line onto a second bit line associated with a set of said first bit lines; whereby the load that must be driven during a memory cell access operation is less than the load of the total of said set of said first bit lines.
References Cited (Backward Citations)
No citation records indexed.
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