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EP0592111A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

Multichip module integrated circuit device having maximum input/output capability

Assignee: Aptix Corp
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Filing: 1993-09-09
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Granted: —
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Expires: 2013-09-09
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Abstract

Abstract A high I/O count integrated circuit is disposed on a semiconductor chip having opposing faces and comprises a plurality of functional circuit modules, each having inputs and at least one output having a first drive capability. A plurality of a first type of I/O nodes, each comprising a first conductive structure is disposed in a first I/O node array on the surface of a first one of the semiconductor chip faces. A plurality of a second type of I/O nodes, each comprising a first conductive structure is disposed on the first semiconductor chip face. An interconnect architecture comprising a plurality of conductors is superimposed on the functional circuit modules, the interconnect architecture comprises a plurality of interconnect conductors. Selected ones of the interconnect conductors are connectable to the inputs and at least one output of selected ones of the functional circuit modules by electrically programmable user-programmable interconnect elements. Selected ones of the interconnect conductors are connectable to other selected ones of the interconnect conductors by user-programmable interconnect elements. Selected ones of the interconnect conductors are connectable to the first I/O nodes by electrically programmable user-programmable interconnect elements. Selected ones of the interconnect conductors are connectable to the second I/O nodes by electrically programmable user-programmable interconnect elements.

Inventors

  • 👤 Amr Mohsen

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-10-30 17:41
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/90; H10D84/998; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/17704; H10W; H10W20/00; H10W20/40; H10W20/49; H10W70/00; H10W70/60; H10W70/611; H10W70/62; H10W70/641; H10W90/00

Claims Analysis

Total Claims: 4
Claim 1
Independent Claim 278 words
An integrated circuit disposed on a semiconductor chip having opposing faces, said integrated circuit comprising: a plurality of functional circuit modules, each of said functional circuit modules having inputs and at least one output, said at least one output having a first drive capability; a plurality of I/O nodes of a first type, each comprising a first conductive structure disposed in a first I/O node array on the surface of one of said opposing faces of said semiconductor chip; a plurality of I/O nodes of a second type, each comprising a second conductive structure disposed in a second I/O node array on said surface of said one of said opposing faces of said semiconductor chip; a plurality of output buffers, each of said output buffers including an input and an output, said outputs of individual ones of said output buffers connected to a different one of said I/O nodes of a second type and having a second drive capability larger than said first drive capability; an interconnect architecture comprising a plurality of conductors superimposed on said functional circuit modules, said interconnect architecture comprising a plurality of interconnect conductors, selected ones of said interconnect conductors connectable to said inputs and at least one output of selected ones of said functional circuit modules by electrically programmable user-programmable interconnect elements, selected ones of said interconnect conductors connectable to other selected ones of said interconnect conductors by user-programmable interconnect elements, selected ones of said interconnect conductors connectable to said first I/O nodes by electrically programmable user-programmable interconnect elements, and selected ones of said interconnect conductors connectable to the inputs of selected ones of said output buffers by electrically programmable user-programmable interconnect elements.
Claim 2
Dependent Claim 39 words
The integrated circuit of claim 1 wherein said plurality of I/O nodes of said first and second types each comprise a plurality of mounting bumps disposed on said surface of one of said opposing faces of said semiconductor chip.
Claim 3
Dependent Claim 384 words
A multichip module assembly comprising: a multichip module substrate including a plurality of external leads; a plurality of integrated circuits disposed on said multichip module substrate, each of said integrated circuits disposed on a semiconductor chip having opposing faces and comprising a plurality of functional circuit modules, each of said functional circuit modules having inputs and at least one output, said at least one output having a first drive capability, a plurality of I/O nodes of a first type, each comprising a first conductive structure disposed in a first I/O node array on the surface of one of said opposing faces of said semiconductor chip, a plurality of I/O nodes of a second type, each comprising a second conductive structure disposed in a second I/O node array on said surface of said one of said opposing faces of said semiconductor chip, a plurality of output buffers, each of said output buffers including an input and an output, said outputs of individual ones of said output buffers connected to a different one of said I/O nodes of a second type and having a second drive capability larger than said first drive capability, an interconnect architecture comprising a plurality of conductors superimposed on said functional circuit modules, said interconnect architecture comprising a plurality of interconnect conductors, selected ones of said interconnect conductors connectable to said inputs and at least one output of selected ones of said functional circuit modules by electrically programmable user-programmable interconnect elements, selected ones of said interconnect conductors connectable to other selected ones of said interconnect conductors by user-programmable interconnect elements, selected ones of said interconnect conductors connectable to said first I/O nodes by electrically programmable user-programmable interconnect elements, and selected ones of said interconnect conductors connectable to the inputs of selected ones of said output buffers by electrically programmable user-programmable interconnect elements; a plurality of first conductive traces disposed in said multichip module substrate, individual ones of said first conductive traces connected between selected ones of said plurality of I/O nodes of first and second types of said integrated circuits; and a plurality of second conductive traces disposed in said multichip module substrate, individual ones of said second conductive traces connected between selected ones of said plurality of I/O nodes of said second type of said integrated circuits and said external leads.
Claim 4
Dependent Claim 112 words
The multichip module assembly of claim 3, further including a plurality of programmable interconnect structures disposed on said multichip module substrate, each of said programmable interconnect structures including a plurality of input/output connections, and each one of said programmable interconnect structures further including connecting means for connecting together selected ones of said input/output connections, each one of said programmable interconnect means associated with a group of said integrated circuits by conductive traces disposed in said multichip module substrate connected between selected ones of input/output nodes of said programmable interconnect structures and selected ones of said plurality of I/O nodes of a first type of each of its associated group of integrated circuits.

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