Abstract A non-volatile memory cell of the present invention includes: a semiconductor layer of a first conductivity type having an upper portion; a source region (24) of a second conductivity type and a drain region (25) of the second conductivity type which are provided in the upper portion of the semiconductor layer at a certain distance from each other; a channel region provided between the source region (24) and the drain region (25) in the upper portion of the semiconductor layer; an insulating film (13) provided on the upper portion of the semiconductor layer, having a first portion (13a) covering the source region (24), a second portion (13b) covering the drain region (25), and a third portion (13c) covering the channel region; a first floating gate electrode (17a) provided on the first portion (13a) of the insulating film; a second floating gate electrode (17b) provided on the second portion (13b) of the insulating film; and a control gate electrode (14) provided on the third portion of the insulating film (13c) and electrically insulated from the first and second floating gate electrodes (17a,17b), wherein at least one of the first portion (13a) and the second portion (13b) of the insulating film is smaller than that of the third portion (13c) of the insulating film, and wherein part of electric carriers in the source region (24) and/or the drain region (25) are injected into the first floating gate electrode (17a) and/or the second floating gate electrode (17b) through the first portion (13a) and/or second portion (13b) of the insulating film at the time of writing data.
A non-volatile memory cell comprising: a semiconductor layer of a first conductivity type having an upper portion; a source region of a second conductivity type and a drain region of the second conductivity type which are provided in the upper portion of the semiconductor layer at a certain distance from each other; a channel region provided between the source region and the drain region in the upper portion of the semiconductor layer; an insulating film provided on the upper portion of the semiconductor layer, having a first portion covering the source region, a second portion covering the drain region, and a third portion covering the channel region; a first floating gate electrode provided on the first portion of the insulating film; a second floating gate electrode provided on the second portion of the insulating film; and a control gate electrode provided on the third portion of the insulating film and electrically insulated from the first and second floating gate electrodes, wherein at least one of the first portion and the second portion of the insulating film is smaller than that of the third portion of the insulating film, and wherein part of electric carriers in the source region and/or the drain region are injected into the first floating gate electrode and/or the second floating gate electrode through the first portion and/or second portion of the insulating film at a time of writing data.
Claim 2
Dependent Claim
37 words
A non-volatile memory cell according to claim 1, wherein the thickness of both of the first portion and the second portion of the insulating film is smaller than that of the third portion of the insulating film.
Claim 3
Dependent Claim
31 words
A non-volatile memory cell according to claim 2, wherein the thickness of the first portion of the insulating film is equal to that of the second portion of the insulating film.
Claim 4
Dependent Claim
31 words
A non-volatile memory cell according to claim 2, wherein the thickness of the first portion of the insulating film is larger than that of the second portion of the insulating film.
Claim 5
Dependent Claim
124 words
A method for writing either one of three logic data: "0", "1" and "2" in a non-volatile memory cell according to claim 4, comprising the steps of: injecting part of the electric carriers in the source region into the first floating gate electrode through the first portion of the insulating film by applying a first voltage between the control gate electrode, and the source region and the drain region at a time of writing the data "1"; and injecting part of the electric carriers in the source region and the drain region into the first floating gate electrode and the second floating gate electrode through the first portion and the second portion of the insulating film at the time of writing the data "2".
Claim 6
Dependent Claim
18 words
A non-volatile memory cell according to claim 1, wherein the control gate electrode completely covers the channel region.
Claim 7
Dependent Claim
39 words
A non-volatile memory cell according to claim 1, wherein the control gate electrode covers a part of the channel region, and at least one of the first and second floating gate electrodes covers another part of the channel region.
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