Apparatus for computing power consumption of MOS transistor logic function block
Abstract
Abstract Apparatus for computing power consumption in an MOS transistor logic function block include circuit information deriving means for deriving circuit information appropriate for a logic function block of interest based on input and output varying signals to and from said logic function block, load capacitance data, and a net list, slew rate determining means for determining an input slew rate based on information from said circuit information deriving means, a memory section containing expressions for use in computation of power consumption caused by through-current, each expression corresponding to a different one of various types of logic function blocks and representing power consumption caused by through-current as a function of a slew rate and load capacitance, and means for determining power consumption due to through-current by substituting the slew rate as determined by said slew rate determining means and load capacitance data into the computation expression as read from said memory section.
Inventors
- 👤 Naoko c/o Mitsubishi Denki K. K. Omori
- 👤 Michio C/O Mitsubishi Denki K.K. Komoda
Bibliographic Details
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