Patent EP0581246A2 successfully refreshed from Google Patents.
EP0581246A2
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EP
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MOS-type semiconductor device
Assignee: Fuji Electric Co Ltd
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Filing: 1993-07-27
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Granted: —
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Expires: 2013-07-27
Abstract
Abstract In a semiconductor device, in addition to a first emitter layer, a second emitter layer is formed on the surface side of a p-type base in spaced-apart relation with the first emitter layer. The first emitter layer is the source region of a first MOSFET, while the second emitter layer is the source region of a second MOSFET. Through signals imparted to first and second gate electrodes, the device, when turned on, operates with a low on-voltage in a thyristor state and, when turned off, undergoes a turn-off in a short time by changing to a transistor state. The main current in the transistor state flows by being offset toward the first emitter layer side with respect to a main-current path on the lower side of the second emitter layer in the thyristor state. Since the current paths in each mode are separated, it is possible to reduce the resistance in the current path in the transistor state without increasing the on-voltage, thereby making it possible to obtain a large latch-up withstanding capacity.
Inventors
- 👤 Masahito C/O Fuji Electric Co. Ltd. Ohtsuki
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-02 15:50
CPC Classifications
H; H10; H10D; H10D18/00; H10D18/60; H10D18/65; H10D18/655; H10D12/00; H10D12/411; H10D12/441
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
139 words
A semiconductor device, comprising: a thyristor structure comprising a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a third semiconductor region of the first conductivity type, and a fourth semiconductor region of the second conductivity type; a first MISFET capable of injecting majority carriers into said second semiconductor region of the second conductivity type; and a second MISFET capable of being opened or closed independently of said first MISFET and capable of drawing out majority carriers from said third semiconductor region of the first conductivity type, wherein said fourth semiconductor region of the second conductivity type comprises a first source region of said first MISFET and a second source region of said second MISFET, said second source region being formed at a position spaced apart from said first source region.
Claim 2
Dependent Claim
73 words
A semiconductor device according to Claim 1, wherein a drain region of said second MISFET is formed between said first source region of said first MISFET and said second source region of said second MISFET, and shortcircuiting means for making conductive both said drain region of said second MISFET and said third semiconductor region is provided between said first source region of said first MISFET and said drain region of said second MISFET.
Claim 3
Dependent Claim
31 words
A semiconductor device according to Claim 2, wherein said shortcircuiting means is a shortcircuiting electrode which electrically contacts with said drain region and a main surface of said third semiconductor region.
Claim 4
Dependent Claim
50 words
A semiconductor device according to Claim 1, wherein, in said third semiconductor region, a high-concentration semiconductor region of the first conductivity type is disposed between a region where a gate electrode of said first MISFET is disposed and a region where a gate electrode of said second MISFET is disposed.
Claim 5
Dependent Claim
96 words
A semiconductor device according to Claim 4, wherein said third semiconductor region includes said semiconductor region where said gate electrode of said first MISFET is disposed, said high-concentration semiconductor region, and said semiconductor region where said gate electrode of said second MISFET is disposed, and has such relation of impurity concentrations that an impurity concentration of said high-concentration semiconductor region > an impurity concentration of said semiconductor region where said gate electrode of said first MISFET is disposed ≧ an impurity concentration of said semiconductor region where said gate electrode of said second MISFET is disposed.
Claim 6
Dependent Claim
36 words
A semiconductor device according to Claim 1, wherein a dosage in said third semiconductor region of the first conductivity type is not less than 6 x 10¹² cm⁻² and not more than 1.2 x 10¹⁴ cm⁻².
Claim 7
Dependent Claim
28 words
A semiconductor device according to Claim 1, wherein a diffusion depth of said third semiconductor region is not less than 2 µm and not more than 8.5 µm.
Claim 8
Dependent Claim
36 words
A semiconductor device according to Claim 4, wherein a dosage in said high-concentration semiconductor region of the first conductivity type is not less than 1 x 10¹³ cm⁻² and not more than 1 x 10¹⁶ cm⁻².
Claim 9
Dependent Claim
26 words
A semiconductor device according to Claim 1, wherein a diffusion depth of said first source region of said first MISFET is not more than 1.1 µm.
Claim 10
Dependent Claim
38 words
A semiconductor device according to Claim 1, further comprising voltage increasing means for increasing a potential of said first source region of said first MISFET by a predetermined potential as compared with a potential of said second MISFET.
Claim 11
Dependent Claim
28 words
A semiconductor device according to Claim 10, wherein said voltage increasing means is a high-resistance polycrystalline silicon layer connected to said first source region of said first MISFET.
Claim 12
Dependent Claim
26 words
A semiconductor device according to Claim 10, wherein said voltage increasing means is a diffusion resistance of said first source region itself of said first MISFET.
Claim 13
Dependent Claim
36 words
A semiconductor device according to Claim 10, wherein said voltage increasing means is a Schottky junction constituted by said first source region of said first MISFET and a metal electrode formed on said first source region.
Claim 14
Dependent Claim
19 words
A semiconductor device according to Claim 1, wherein said gate electrode of said second MISFET is a metal gate.
Claim 15
Dependent Claim
19 words
A semiconductor device according to Claim 1, wherein said gate electrode of said second MISFET is a silicide gate.
Claim 16
Dependent Claim
122 words
A semiconductor device according to Claim 1, wherein a chip of said semiconductor device comprises a first gate main wiring disposed along one side of said chip, a second gate main wiring disposed along an opposing side of said chip, a first branch line in a form of comb teeth branching out from said first gate main wiring, and a second branch line in a form of comb teeth branching out from said first gate main wiring, and wherein two strips of said second branch line are placed between adjacent two strips of said first branch line, said first branch line being said gate electrode of said first MISFET, and said second branch line being said gate electrode of said second MISFET.
Claim 17
Dependent Claim
145 words
A semiconductor device according to Claim 1, wherein a chip of said semiconductor device comprises a first gate main wiring disposed along one side of said chip, a second gate main wiring disposed along an opposing side of said chip; a first branch line in a form of comb teeth branching out from said first gate main wiring, and a second branch line in a form of comb teeth branching out from said first gate main wiring, and wherein said gate electrode of said second MISFET for each cell of said chip has a ring-shaped configuration connected to said second branch line, said gate electrode of said first MISFET for said each cell being connected to said first branch line and being formed in such a manner as to surround an outer side of said gate electrode of said second MISFET in a ring-shaped configuration.
Claim 18
Dependent Claim
138 words
A semiconductor device according to Claim 1, wherein a chip of said semiconductor device comprises a first gate main wiring disposed along one side of said chip, a second gate main wiring disposed along an opposing side of said chip; a first branch line in a form of comb teeth branching out from said first gate main wiring, and a second branch line in a form of comb teeth branching out from said first gate main wiring, and wherein said gate electrode of said first MISFET for each cell of said chip is connected to said first branch line, said gate electrode of said second MISFET for said each cell being connected to said second branch line and being formed in such a manner as to surround an outer side of said gate electrode of said first MISFET.
Claim 19
Dependent Claim
27 words
A semiconductor device according to Claim 18, wherein said gate electrode of said first MISFET for said each cell is formed in a configuration of a ring.
Claim 20
Dependent Claim
36 words
A semiconductor device according to Claim 1, wherein a source electrode wiring of said first MISFET and a source electrode wiring of said second MISFET are formed by a single-layered wiring structure of an identical layer.
Claim 21
Dependent Claim
35 words
A semiconductor device according to Claim 1, wherein a source electrode wiring of said first MISFET and a source electrode wiring of said second MISFET are formed by a two-layered wiring structure of different layers.
References Cited (Backward Citations)
No citation records indexed.
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