Compact phase recovery scheme using digital circuits

Claim 2

A retiming circuit for synchronizing a digital input signal with a local clock, comprising: a delay means for delaying said digital input signal which is responsive to a digital control signal wherein said digital control signal controls a delay added to said digital input signal; a phase comparator means connected to said delay means and said local clock for comparing a phase of said local clock with a phase of said delayed input signal and generating a digital phase comparator signal which corresponds to said phase comparison; and a digital filter connected to said phase comparator and to said delay means for controlling said delay means, said digital filter generates said digital control signal for said delay means in response to said phase comparator signal.

Claim 3

A phase lock loop, comprising: a phase comparator connected to a digital filter and a voltage controlled oscillator, said phase comparator having a digital data input signal and a digital input signal from said voltage controlled oscillator, said phase comparator generates a digital phase comparator signal which corresponds to a phase difference between said data signal and said voltage controlled oscillator signal; said digital filter having a digital data input signal, said phase comparator transmits said phase comparator signal to said digital filter, said digital filter generates a digital control signal from said phase comparator signal and said digital data input signal; a digital to analog converter connected to said digital filter, said phase comparator, and said voltage controlled oscillator, said phase comparator transmits said phase comparator signal to said digital to analog converter, said digital filter transmits said digital control signal to said digital to analog converter, said digital to analog converter converts said digital control signal to an analog control signal to control said voltage controlled oscillator, said digital to analog converter transmits said analog control signal to said voltage controlled oscillator, said voltage controlled oscillator generates a digital input signal having a frequency corresponding to said analog control signal; and said voltage controlled oscillator transmits said digital input signal to said phase comparator.

Claim 4

A structure, as in claim 2 or 3, wherein: said digital filter comprises a prescaler means for grouping a plurality of digital pulses into a plurality of groups of digital pulses, each of said plurality of groups of digital pulses having an identical number of digital pulses, said prescaler generates a plurality of first increment or first decrement signals from said plurality of groups of digital pulses; and a counter means coupled to said prescaler means for counting said first increment and decrement signals generated by said prescaler and generating a digital control signal corresponding to said count of said first increment and decrement signals.

Claim 5

A structure, as in one of claims 1 to 4, wherein: said prescaler means groups said plurality of digital pulses into groups of two digital pulses; and said prescaler means generates a first increment signal when two digital pulses in one of said plurality of groups of digital pulses have a first polarity and said prescaler means generates a first decrement signal when two of said digital pulses in one of said plurality of groups of digital pulses have a second polarity.

Claim 6

A structure, as in one of claims 1 to 4, wherein: said prescaler means groups said plurality of digital pulses into groups of four digital pulses.

Claim 7

A structure, as in one of claims 1 to 6, wherein: said counter means comprises a first counter means for counting said first increment and decrement signals from said prescaler means and a second counter means for generating said digital signal output; said prescaler means increments said first counter means when said prescaler means generates a first increment signal, said prescaler means decrements said first counter means when said prescaler generates a first decrement signal; said first counter means generates a second increment signal when said first counter means counts higher than a first counter limit, said first counter means generates a second decrement signal when said first counter means counts lower than a second counter limit; said first counter means is reset to an intermediate value when said first counter means is greater than said first counter limit, said first counter means is reset to an intermediate value when said first counter means is less than said second counter limit; and said second increment signal increments said second counter means and said second decrement signal decrements said second counter means.

Claim 8

A process for filtering a digital signal, comprising: grouping a plurality of digital pulses into a plurality of groups of digital pulses, each of said plurality of groups of digital pulses having an identical number of digital pulses; generating a plurality of first increment or decrement signals from said plurality of groups of digital pulses; counting said first increment and decrement signals; and generating a digital output signal corresponding to said count of said first increment and decrement signals.

Claim 9

A process for filtering a digital signal, as in claim 8, wherein: each of said plurality of groups of digital pulses has two digital pulses; and said first increment signal is generated when two digital pulses in one of said plurality of groups of digital pulses have a first polarity, and said first decrement signal is generated when two digital pulses in one of said plurality of groups of digital pulses have a second polarity.

Claim 10

A process for filtering a digital signal, as in claim 8, wherein: each of said plurality of groups of digital pulses has four digital pulses.

Claim 11

A process for filtering a digital signal, as in one of the claims 8 to 10, further comprising: generating a second increment and decrement signal from said counting of said first increment and decrement signals, said second increment signal is generated when said counting of said first increment and decrement signals counts greater than a first counter limit, said second decrement signal is generated when said counting of said first increment and decrement signals counts lower than a second counter limit; counting said second increment and decrement signals; and generating said digital signal output from said second increment and decrement signals.

Claim 12

A clock generator circuit for generating four timing pulses from an input data signal, comprising: a first latch having said data input signal as an input; a second latch having a complement of said data input signal as an input, a true output from said first latch forming a second input to said second latch; a complement output from said second latch forms a second input to said first latch; a first logical AND gate having said true output of said first latch and a true output of said second latch as inputs wherein an output from said first AND gate forms a first timing pulse; a second logical AND gate having said complement output from said second latch and a complement output from said first latch as inputs wherein an output from said second AND gate forms a third timing pulse, said third timing pulse does not overlap said first timing pulse; a third logical AND gate having said complement output of said first latch and said true output of said second latch as inputs wherein an output of said third logical AND gate forms a second timing pulse; and a fourth logical AND gate having said true output of said first latch and said complement output of said second latch as inputs wherein an output from said fourth AND gate forms a fourth timing pulse, said fourth timing pulse does not overlap said second timing pulse.

Claim 13

A process for generating four timing pulses from a digital data input signal, comprising: combining a true output from a first latch and a true output from a second latch in an AND function to form a first timing pulse wherein said first latch has a digital data input signal as a first input, said second latch has a complement of said digital data input signal as a first input, said second latch having a complement output connected to a second input of said first latch, and said first latch having a true output connected to a second input of said second latch; combining a complement output from said first latch and a complement output from said second latch in an AND function to form a third timing pulse wherein said first timing pulse and said third timing pulse do not overlap; combining a complement output from said first latch and a true output from said second latch in an AND function to form a second timing pulse; and combining a true output from said first latch and a complement output from said second latch in an AND function to form a fourth timing pulse wherein said second timing pulse and said fourth timing pulse do not overlap.

Claim 14

A digital filter, comprising: a clock generator circuit for generating four timing pulses from an input data signal; a prescaler means for grouping a plurality of digital pulses into a plurality of groups of digital pulses, each of said plurality of groups digital pulses having two digital pulses, said prescaler generates a plurality of first increment or first decrement signals from said plurality of groups of digital pulses, said prescaler means being updated by a first timing pulse from said clock generator circuit; a first counter means coupled to said prescaler means for counting said first increment and decrement pulses generated by said prescaler, said first counter means having master and slave latches, said master latches being updated by a third timing pulse generated from said clock generator circuit and said slave latches being updated from said first timing pulse, said first and third timing pulses do not overlap; and a second counter means coupled to said first counter means for generating a digital signal output corresponding to said count of said first increment and decrement signals, said second counter means having master and slave latches, said master latches of said second counter means being updated by said first timing pulse and said slave latches of said second counter means being updated by said third timing pulse.

Claim 15

A digital filter, comprising: a clock generator circuit for generating four timing pulses from an input data signal; a prescaler means for grouping a plurality of digital pulses into a plurality of groups of digital pulses, each of said plurality of groups digital pulses having four digital pulses, said prescaler generates a plurality of first increment or first decrement signal from said plurality of groups of digital pulses, said prescaler means being updated by a fourth timing pulse from said clock generator circuit; a first counter means coupled to said prescaler means for counting said first increment and decrement pulses generated by said prescaler, said first counter means having master and slave latches, said master latches being updated by a second timing pulse generated from said clock generator circuit and said slave latches being updated from said fourth timing pulse, said second and fourth timing pulses do not overlap; and a second counter means coupled to said first counter means for generating a digital signal output corresponding to said count of said first increment and decrement signals, said second counter means having master and slave latches, said master latches of said second counter means being updated by said fourth timing pulse and said slave latches of said second counter means being updated by said second timing pulse.

Claim 16

A retiming circuit as in claim 2 wherein: said digital filter includes a clock generator circuit, a prescaler means, a first counter means, and a second counter means, said clock generator circuit generates four timing pulses from said delayed input data signal; said prescaler means groups a plurality of digital pulses from said phase comparator into a plurality of groups of digital pulses, each of said plurality of groups digital pulses having two digital pulses, said prescaler generates a plurality of first increment or first decrement signal from said plurality of groups of digital pulses, said prescaler means being updated by a first timing pulse from said clock generator circuit; said first counter means coupled to said prescaler means counts said first increment and decrement pulses generated by said prescaler, said first counter means having master and slave latches, said master latches being updated by a third timing pulse generated from said clock generator circuit and said slave latches being updated from said first timing pulse, said first and third timing pulses do not overlap; and said second counter means coupled to said first counter means generates a digital signal output corresponding to said count of said first increment and decrement signals, said second counter means having master and slave latches, said master latches of said second counter means being updated by said first timing pulse and said slave latches of said second counter means being updated by said third timing pulse.

Claim 17

A retiming circuit as in claim 2 comprising: said digital filter includes a clock generator circuit, a prescaler means, a first counter means, and a second counter means, said clock generator circuit generates four timing pulses from said delayed input data signal; said prescaler means groups a plurality of digital pulses from said phase comparator into a plurality of groups of digital pulses, each of said plurality of groups digital pulses having four digital pulses, said prescaler generates a plurality of first increment or first decrement signals from said plurality of groups of digital pulses, said prescaler means being updated by a fourth timing pulse from said clock generator circuit; said first counter means coupled to said prescaler means counts said first increment and decrement pulses generated by said prescaler, said first counter means having master and slave latches, said master latches being updated by a second timing pulse generated from said clock generator circuit and said slave latches being updated from said fourth timing pulse, said second and fourth timing pulses do not overlap; and said second counter means coupled to said first counter means generates a digital signal output corresponding to said count of said first increment and decrement signals, said second counter means having master and slave latches, said master latches of said second counter means being updated by said fourth timing pulse and said slave latches of said second counter means being updated by said second timing pulse.

Claim 18

A phase lock loop, comprising: a phase comparator connected to a digital filter and a voltage controlled oscillator, said phase comparator having a digital data input signal and a digital input signal from said voltage controlled oscillator, said phase comparator generates a digital phase comparator signal which corresponds to a phase difference between said data signal and said voltage controlled oscillator signal; said digital filter having a digital data input signal, said phase comparator transmits said phase comparator signal to said digital filter, said digital filter generates a digital control signal from said phase comparator signal and said digital data input signal, said digital filter comprising a clock generator circuit, a prescaler, a first counter means, and a second counter means; said clock generator circuit generates four timing pulses from said input data signal; said prescaler means groups a plurality of digital pulses from said phase comparator into a plurality of groups of digital pulses, each of said plurality of groups digital pulses having two digital pulses, said prescaler generates a plurality of first increment or first decrement signal from said plurality of groups of digital pulses, said prescaler means being updated by a first timing pulse from said clock generator circuit; said first counter means coupled to said prescaler means counts said first increment and decrement pulses generated by said prescaler, said first counter means having master and slave latches, said master latches being updated by a third timing pulse generated from said clock generator circuit and said slave latches being updated from said first timing pulse, said first and third timing pulses do not overlap; said second counter means coupled to said first counter means generates a digital signal output corresponding to said count of said first increment and decrement signals, said second counter means having master and slave latches, said master latches of said second counter means being updated by said first timing pulse and said slave latches of said second counter means being updated by said third timing pulse; a digital to analog converter connected to said digital filter, said phase comparator, and said voltage controlled oscillator, said phase comparator transmits said phase comparator signal to said digital to analog converter, said digital filter transmits said digital control signal to said digital to analog converter, said digital to analog converter converts said digital control signal to an analog control signal to control said voltage controlled oscillator, said digital to analog converter transmits said analog control signal to said voltage controlled oscillator, said voltage controlled oscillator generates a digital input signal having a frequency corresponding to said analog control signal; and said voltage controlled oscillator transmits said digital input signal to said phase comparator.

Claim 19

A phase lock loop, comprising: a phase comparator connected to a digital filter and a voltage controlled oscillator, said phase comparator having a digital data input signal and a digital input signal from said voltage controlled oscillator, said phase comparator generates a digital phase comparator signal which corresponds to a phase difference between said data signal and said voltage controlled oscillator signal; said digital filter having a digital data input signal, said phase comparator transmits said phase comparator signal to said digital filter, said digital filter generates a digital control signal from said phase comparator signal and said digital data input signal, said digital filter includes a clock generator circuit, a prescaler, a first counter means, and a second counter means; said clock generator circuit for generates four timing pulses from said input data signal; said prescaler means groups a plurality of digital pulses from said phase comparator into a plurality of groups of digital pulses, each of said plurality of groups digital pulses having four digital pulses, said prescaler generates a plurality of first increment or first decrement signal from said plurality of groups of digital pulses, said prescaler means being updated by a fourth timing pulse from said clock generator circuit; said first counter means coupled to said prescaler means counts said first increment and decrement pulses generated by said prescaler, said first counter means having master and slave latches, said master latches being updated by a second timing pulse generated from said clock generator circuit and said slave latches being updated from said fourth timing pulse, said second and fourth timing pulses do not overlap; said second counter means coupled to said first counter means generates a digital signal output corresponding to said count of said first increment and decrement signals, said second counter means having master and slave latches, said master latches of said second counter means being updated by said fourth timing pulse and said slave latches of said second counter means being updated by said second timing pulse; a digital to analog converter connected to said digital filter, said phase comparator, and said voltage controlled oscillator, said phase comparator transmits said phase comparator signal to said digital to analog converter, said digital filter transmits said digital control signal to said digital to analog converter, said digital to analog converter converts said digital control signal to an analog control signal to control said voltage controlled oscillator, said digital to analog converter transmits said analog control signal to said voltage controlled oscillator, said voltage controlled oscillator generates a digital input signal having a frequency corresponding to said analog control signal; and said voltage controlled oscillator transmits said digital input signal to said phase comparator.