Semiconductor integrated circuit with input/output interface adapted for small-amplitude operation

Claim 2

A semiconductor integrated circuit comprising: switch means for controlling the supply of a power source voltage to a signal amplification circuit receiving an input signal; and control means for selectively turning ON and OFF said switch means in accordance with the amplitude or frequency of said input signal.

Claim 3

A semiconductor integrated circuit according to claim 1, wherein said switch means is a transistor, and said input signal is applied to the gate of said transistor through a resistance element having a value greater than an impedance matching load resistance value of an external signal bus line.

Claim 4

A semiconductor integrated circuit comprising: a pair of differential transistors for applying an input signal changing at a first frequency or at a second frequency lower than said first frequency to one of the control electrodes, and applying a reference voltage substantially corresponding to an intermediate value of a logical amplitude of said input signal to the other of said control electrodes; a low potential side transistor interposed between a pair of said differential transistors and a low potential side power source; a high potential side transistor interposed between said differential transistor and an active load or between said active load and a high potential side power source; first control voltage generation means for generating a control voltage which turns ON both of said low potential side transistor and said high potential side transistor irrespective of the logical state of said input signal when the frequency of said input signal exists near said first frequency; and second control voltage generation means for generating a control voltage which turns ON one of said low potential side transistor and said high potential side transistor in accordance with the logical state of said input signal when the frequency of said input signal exists near said second frequency.

Claim 5

A semiconductor integrated circuit comprising: a pair of differential transistors for applying an input signal changing at a first frequency or at a second frequency lower than said first frequency to one of the control electrodes, and applying a reference voltage substantially corresponding to an intermediate value of a logical amplitude of said input signal to the other of said control electrodes; a low potential side transistor interposed between a pair of said differential transistors and a low potential side power source; a high potential side transistor interposed between said differential transistor and an active load or between said active load and a high potential side power source; first control voltage generation means for generating a control voltage which turns ON both of said low potential side transistor and said high potential side transistor irrespective of the logical state of said input signal when the frequency of said input signal exists near said first frequency; and second control voltage generation means for generating a control voltage which turns ON one of said low potential side transistor and said high potential side transistor in accordance with the logical state of said input signal when the frequency of said input signal exists near said second frequency.

Claim 6

A semiconductor integrated circuit comprising: a comparator circuit for detecting high and low levels of an input voltage with reference to a reference voltage; and an input circuit including first and second transistors for controlling a power source current to said comparator circuit, interposed between first and second power sources and said comparator circuit, respectively, wherein an input signal applied to said comparatorcircuit is also applied to said first and second transistors.

Claim 7

A semiconductor integrated circuit comprising: a comparator circuit for detecting high and low levels of an input voltage with reference to a reference voltage; and an input circuit including first and second transistors for controlling a power source current to said comparator circuit, interposed between first and second power sources and said comparator circuit, respectively, wherein an input signal applied to said comparatorcircuit is also applied to said first and second transistors.

Claim 8

A semiconductor integrated circuit comprising: a pair of differential transistors for applying an input signal having a first logical amplitude or a second logical amplitude greater than said first logical amplitude to one of the control electrodes, and applying a reference voltage substantially corresponding to an intermediate value of the logical amplitude of said input signal to the other of said control electrodes; a low potential side transistor interposed between a pair of said differential transistors and a low potential side power source; a high potential side transistor interposed between said differential transistors and an active load or between said active load and a high potential side power source; and said input signal being applied to the control electrode of each of said low potential side transistor and said high potential side transistor.

Claim 9

A semiconductor integrated circuit comprising: a pair of differential transistors for applying an input signal having a first logical amplitude or a second logical amplitude greater than said first logical amplitude to one of the control electrodes, and applying a reference voltage substantially corresponding to an intermediate value of the logical amplitude of said input signal to the other of said control electrodes; a low potential side transistor interposed between a pair of said differential transistors and a low potential side power source; a high potential side transistor interposed between said differential transistors and an active load or between said active load and a high potential side power source; and said input signal being applied to the control electrode of each of said low potential side transistor and said high potential side transistor.

Claim 10

A semiconductor integrated circuit comprising: a transmission line for transmitting an input signal; a voltage source for generating a voltage substantially corresponding to an intermediate value of a logical amplitude of said input signal; a terminal resistor interposed between said transmission line and said voltage source through predetermined switching means; and ON/OFF control means for turning ON said switching means when the frequency of said input signal corresponds to said first frequency, and turning OFF said switching means when the frequency of said input signal corresponds to said second frequency.

Claim 11

A semiconductor integrated circuit comprising: a transmission line for transmitting an input signal; a voltage source for generating a voltage substantially corresponding to an intermediate value of a logical amplitude of said input signal; a terminal resistor interposed between said transmission line and said voltage source through predetermined switching means; and ON/OFF control means for turning ON said switching means when the frequency of said input signal corresponds to said first frequency, and turning OFF said switching means when the frequency of said input signal corresponds to said second frequency.

Claim 12

A semiconductor integrated circuit including: a first PMOS transistor (230a) and a first NMOS transistor (230b), connected in series between a high potential side power source (Vcc) and a low potential side power source (Vss); a second PMOS transistor (231a) and a second NMOS transistor (231 b), connected in series between said high potential side power source (Vcc) and said low potential side power source (Vss); and ON/OFF control means (233) for selectively turning ON and OFF said four transistors (230a, 230b, 231a, 231 b) in accordance with a signal logic from a chip internal circuit (232); wherein a junction (P 200 ) between said first PMOS transistor (230a) and said first NMOS transistor (230b) as well as a junction (P 201 ) between said second PMOS transistor (231a) and said second NMOS transistor (231 b) are connected to a signal line (234) outside the chip, and said signal line (234) is connected to either said high potential side power source (Vcc) or said low potential side power source (Vss) by the selective ON/OFF operation of said four transistors (230a, 230b, 231 a, 231 b); said semiconductor integrated circuit comprising: mode control means (236) for executing control in such a manner that when a mode designation signal (CMOS) represents a first transfer mode in which a terminal resistor (235) is connected and used between said signal line (234) and a predetermined constant voltage (V TT ,), said first PMOS transistor (230a) or said NMOS transistor (230b) drives said signal line (234), and when said mode designation signal (CMOS) represents a second transfer mode in which said terminal resistor (235) is not connected, said second PMOS transistor (231a) or said second NMOS transistor (231 b) drives said signal line (234); and the ON resistance of said first PMOS transistor (230a) and said first NMOS transistor (230b) being set on the basis of a signal amplitude on said signal line (234) during said first transfer mode and a value of said terminal resistor (235), and the ON resistance of said second PMOS transistor (231a) and said second NMOS transistor (231 b) being set on the basis of the signal amplitude on said signal line (234) during said second transfer mode.

Claim 13

A semiconductor integrated circuit including: a first PMOS transistor (230a) and a first NMOS transistor (230b), connected in series between a high potential side power source (Vcc) and a low potential side power source (Vss); a second PMOS transistor (231a) and a second NMOS transistor (231 b), connected in series between said high potential side power source (Vcc) and said low potential side power source (Vss); and ON/OFF control means (233) for selectively turning ON and OFF said four transistors (230a, 230b, 231a, 231 b) in accordance with a signal logic from a chip internal circuit (232); wherein a junction (P 200 ) between said first PMOS transistor (230a) and said first NMOS transistor (230b) as well as a junction (P 201 ) between said second PMOS transistor (231a) and said second NMOS transistor (231 b) are connected to a signal line (234) outside the chip, and said signal line (234) is connected to either said high potential side power source (Vcc) or said low potential side power source (Vss) by the selective ON/OFF operation of said four transistors (230a, 230b, 231 a, 231 b); said semiconductor integrated circuit comprising: mode control means (236) for executing control in such a manner that when a mode designation signal (CMOS) represents a first transfer mode in which a terminal resistor (235) is connected and used between said signal line (234) and a predetermined constant voltage (V TT ,), said first PMOS transistor (230a) or said NMOS transistor (230b) drives said signal line (234), and when said mode designation signal (CMOS) represents a second transfer mode in which said terminal resistor (235) is not connected, said second PMOS transistor (231a) or said second NMOS transistor (231 b) drives said signal line (234); and the ON resistance of said first PMOS transistor (230a) and said first NMOS transistor (230b) being set on the basis of a signal amplitude on said signal line (234) during said first transfer mode and a value of said terminal resistor (235), and the ON resistance of said second PMOS transistor (231a) and said second NMOS transistor (231 b) being set on the basis of the signal amplitude on said signal line (234) during said second transfer mode.

Claim 14

A semiconductor integrated circuit according to claim 7, wherein said mode control means (236) executes control in such a manner as to drive said signal line (234) by said first PMOS transistor (231a) and said second PMOS transistor (231a), or by said first NMOS transistor (230b) and said second NMOS transistor (231 b), when said mode designation signal (CMOS) designates said second transfer mode.

Claim 15

A semiconductor integrated circuit according to claim 7, further comprising: a comparator (601 or 602) for comparing a potential of a reference voltage terminal (607) of a chip with a predetermined constant voltage (VCTT or V GTL ), and generating said mode designation signal in a logical state corresponding to the result of comparison; switch means (603 or 604) adapted to cut off a power source current of said comparator; and said switch means being turned OFF when the potential of said reference voltage terminal of said chip is at a predetermined high potential or is under an open state.

Claim 16

A semiconductor integrated circuit according to claim 7, wherein the potential of said reference terminal of said chip is used as a reference voltage of an input buffer circuit when said mode designation signal designates said first transfer mode, and a predetermined constant voltage is used as the reference voltage of said input buffer circuit when said mode designation signal designates said second transfer mode.

Claim 17

A semiconductor integrated circuit according to claim 7, wherein a third NMOS transistor is connected in parallel with said first NMOS transistor, and when said mode designation signal designates said first transfer mode and moreover, when said first NMOS transistor is turned ON, said third NMOS transistor is simultaneously turned ON.

Claim 18

A semiconductor integrated circuit comprising differential transistors for outputting a signal corresponding to a difference between an input signal having a very small amplitude and a reference potential corresponding to an intermediate amplitude value of said input signal, wherein the threshold values of said differential transistors are mutually different.

Claim 19

A semiconductor integrated circuit comprising differential transistors for outputting a signal corresponding to a difference between an input signal having a very small amplitude and a reference potential corresponding to an intermediate amplitude value of said input signal, wherein the threshold values of said differential transistors are mutually different.

Claim 20

A semiconductor integrated circuit according to claim 12, further comprising potential generation means for generating a potential within a range of a maximum amplitude of said input signal and different from said intermediate amplitude value of said input signal, wherein the potential generated by said potential generation means is used in place of said reference potential.

Claim 21

A semiconductor integrated circuit according to claim 12, further comprising: potential generation means for generating two potentials within a range of a maximum amplitude of said input signal and interposing the intermediate amplitude value of said input signal between them; a first differential amplification unit for differentially amplifying said input signal by the use of a first potential generated by said potential generation means; a second differential amplification unit for differentially amplifying said input signal by the use of a second potential generated by said potential generation means; and selection means for selecting the outputs of said first and second differential amplification units.

Claim 22

A semiconductor integrated circuit according to claim 12, wherein a transistor is used as the load of said differential transistors, and conductivity of said load transistor is controlled by the output of an input circuit inclusive of said differential transistors.

Claim 23

A semiconductor integrated circuit according to claim 15, wherein conductivity of said load transistor is reduced for a predetermined time from the rise and fall timings of the output of said input circuit.

Claim 24

A semiconductor integrated circuit comprising: a PMOS transistor (55 or 57) and an NMOS transistor (56 or 58) connected in series between a high potential side power source (Vcc) and a low potential side power source (Vss); an output terminal (61) taken out from the junction between both of said transistors; first means (41, 42, 43, 45, 46, 47, 53 and 54) for causing a push-pull operation of said PMOS transistor and said NMOS transistor in accordance with a logic of a signal to be outputted; and second means (46 and 47) for cutting off said PMOS transistor in response to a predetermined level designation signal (GTL).

Claim 25

A semiconductor integrated circuit comprising: a PMOS transistor (55 or 57) and an NMOS transistor (56 or 58) connected in series between a high potential side power source (Vcc) and a low potential side power source (Vss); an output terminal (61) taken out from the junction between both of said transistors; first means (41, 42, 43, 45, 46, 47, 53 and 54) for causing a push-pull operation of said PMOS transistor and said NMOS transistor in accordance with a logic of a signal to be outputted; and second means (46 and 47) for cutting off said PMOS transistor in response to a predetermined level designation signal (GTL).

Claim 26

A semiconductor integrated circuit according to claim 17, which further comprises an output circuit including: a first PMOS transistor (55 or 57) and a first NMOS transistor (56 or 58) connected in series between said high potential side power source and said low potential side power source; a second PMOS transistor (57 or 55) and a second NMOS transistor (58 or 56) connected in series between said high potential side power source and said low potential side power source; an output terminal (61) taken out from the junction between said first PMOS transistor and said first NMOS transistor and from the junction between said second PMOS transistor and said second NMOS transistor; third means (52) for detecting determination of a logic state of said junctions or said output terminal; first A means (41, 42, 43, 45, 46, 47, 53 and 54) for turning ON both of said first and second PMOS transistors or both of said first and second NMOS transistors in response to the logical change of said signal to be outputted; and first B means (47 and 53) for turning OFF one of said first and second PMOS transistors or one of said first and second NMOS transistors in response to a determination signal of the output logic from said third means.

Claim 27

A semiconductor integrated circuit according to claim 18, further comprising an output circuit for turning ON both of said first and second NMOS transistors when the logic of said signal to be outputted is an L logic and moreover, when a predetermined level designation signal is active, and turning OFF belatedly either one of said first and second PMOS transistors when the logic of said signal to be outputted is an H logic and moreover, when said predetermined level designation signal is active; said output circuit including fourth means (41,42,43,45,46,47, 53 and 54) for cutting OFF the other of said first PMOS transistor and said second PMOS transistor in response to the determination signal of the output logic from said third means.

Claim 28

A semiconductor integrated circuit according to claim 18, further comprising an output circuit for setting the ON resistance of said transistor among said first and second PMOS transistors, which does not respond to the determination signal of the output logic from said third means, to be higher than the ON resistance of said transistor which responds to the determination signal.

Claim 29

A semiconductor integrated circuit according to claim 18, furthercomprising an output circuit including fifth means (59 and 60) for controlling the turn-on time of said transistor among said first and second PMOS transistors, which does not respond to the determination signal of the output logic from said third means, to be longer than the turn-on time of said transistor.

Claim 30

A semiconductor integrated circuit comprising: a differential gate (10) for comparing a potential of an input signal (V 1N ) with a predetermined reference potential (V REF ) and discriminating the logic of said input signal (V IN ); selection means (13) for selecting eitherone of a first reference potential (V REF1 ) given from outside a chip and a second reference potential (V REF2 ) generated by reference potential generation means (12) inside the chip; and instruction means (14) for instructing siad selection means (13) to select said first reference potential (V REF1 ) when said first reference potential (V REF1 ) is given, and instructing said selection means (13) to select said second reference potential (V REF2 ) when said first reference potential (V REF1 ) is not given.

Claim 31

A semiconductor integrated circuit comprising: a differential gate (10) for comparing a potential of an input signal (V 1N ) with a predetermined reference potential (V REF ) and discriminating the logic of said input signal (V IN ); selection means (13) for selecting eitherone of a first reference potential (V REF1 ) given from outside a chip and a second reference potential (V REF2 ) generated by reference potential generation means (12) inside the chip; and instruction means (14) for instructing siad selection means (13) to select said first reference potential (V REF1 ) when said first reference potential (V REF1 ) is given, and instructing said selection means (13) to select said second reference potential (V REF2 ) when said first reference potential (V REF1 ) is not given.

Claim 32

A semiconductor integrated circuit according to claim 22, wherein said reference potential generation means inside said chip generates said reference potential by a resistor type potential division circuit, and a switch element inserted in series into said resistance type potential division circuit is turned ON and OFF in accordance with the output of said instruction means.

Claim 33

A semiconductor integrated circuit according to claim 22, wherein said selection means is disposed in the most vicinity of said differential gate.

Claim 34

A semiconductor integrated circuit comprising: a logic gate (83) for discriminating a logic of an input signal (VN) by comparing said input signal (V 1N ) with a predetermined input threshold value (V 1NV ); a differential gate (84) for discriminating a logic of said input signal (VN) by comparing said input signal (V IN ) with a reference potential (V REF1 ) given outside the chip; selection means (85) for selecting either one of the output of said logic gate and the output of said differential gate; and instruction mean (86) for instructing said selection means (85) to select the output of said differential gate (84) when said reference potential (V REF1 ) is given, and instructing said selection means (85) to select the output of said logic gate (83) when said reference potential ( REF1 ) is not given.

Claim 35

A semiconductor integrated circuit comprising: a logic gate (83) for discriminating a logic of an input signal (VN) by comparing said input signal (V 1N ) with a predetermined input threshold value (V 1NV ); a differential gate (84) for discriminating a logic of said input signal (VN) by comparing said input signal (V IN ) with a reference potential (V REF1 ) given outside the chip; selection means (85) for selecting either one of the output of said logic gate and the output of said differential gate; and instruction mean (86) for instructing said selection means (85) to select the output of said differential gate (84) when said reference potential (V REF1 ) is given, and instructing said selection means (85) to select the output of said logic gate (83) when said reference potential ( REF1 ) is not given.

Claim 36

A semiconductor integrated circuit comprising: an output circuit for providing a first output voltage (V OH ) for determining an H level to a predetermined reference voltage (V TT ), and a second output voltage (V OL ) for determining an L level; and means for controlling said first and second output voltages under a substantial non-load state to voltage levels having absolute values smaller than the absolute values of voltages corresponding to power sources (V cc , V ss ,; V cc2 , V ss2 ), respectively.

Claim 37

A semiconductor integrated circuit comprising: an output circuit for providing a first output voltage (V OH ) for determining an H level to a predetermined reference voltage (V TT ), and a second output voltage (V OL ) for determining an L level; and means for controlling said first and second output voltages under a substantial non-load state to voltage levels having absolute values smaller than the absolute values of voltages corresponding to power sources (V cc , V ss ,; V cc2 , V ss2 ), respectively.

Claim 38

A semiconductor integrated circuit according to claim 26, wherein said output circuit includes a power source circuit (P1, P2; P3, P4) for receiving an external power source voltage (V cc , V ss ) and said predetermined reference voltage and generating an internal power source voltage smaller than said external power source voltage, and a driving circuit for receiving the supply of said internal power source voltage and providing said first and second output voltages.

Claim 39

A semiconductor integrated circuit according to claim 27, wherein said driving circuit includes a circuit unit (Q5, Q6; Q12 to Q15) having a CMOS structure and operating on receiving the supply of said internal power source voltage, an N channel transistor (Q7) for providing said first output voltage in response to the output of said circuit unit, and a P channel transistor (Q8) for providing said second output voltage in response to the output of said circuit portion.

Claim 40

Asemiconductor integrated circuit according to claim 28, wherein said circuit portion having a CMOS structure includes a set of CMOS transistors (Q5, Q6) operating on receiving the supply of said internal power source voltage, and the gate potentials of said N channel transistor and said P channel transistors are controlled in common by the output of said transistors having a CMOS structure.

Claim 41

A semiconductor integrated circuit according to claim 28, wherein said circuit unit having the CMOS structure includes two sets of CMOS transistors (Q12 to Q15) connected in series, the output of one of the sets of said CMOS transistors controls the gate potential of said N channel transistor, and the output of the other set of said CMOS transistors controls the gate potential of said P channel transistor.

Claim 42

A semiconductor integrated circuit according to claim 30, further comprising a power source circuit (P5) for supplying said reference voltage to the junction between one of said CMOS transistors and the other of said CMOS transistors.

Claim 43

Asemiconductor integrated circuit according to claim 27, wherein said power source circuit includes a plurality of resistors (R5 to R7) connected between lines of an external power source voltage and said reference voltage, switch means (Q20 to Q22) for alternatively selecting a plurality of voltage levels divided by said resistors, and a circuit (OLC) for controlling ON and OFF of said switch means on the basis of control data given from outside, and wherein the voltage level of said internal power source voltage is made variable on the basis of said control data given from outside.

Claim 44

A semiconductor integrated circuit according to claim 26, wherein said predetermined reference voltage (V TT ) is generated inside and is set to an intermediate potential of said external power source voltages (V cc , V ss ).