§
Luxuse
Patent Intelligence
Sign In
Patent EP0574748A2 successfully refreshed from Google Patents.
← Back to Patent Explorer
EP0574748A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

Scalable multimedia platform architecture

Assignee: Intel Corp
•
Filing: 1993-05-26
•
Granted: —
•
Expires: 2013-05-26
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract The scalable platform architecture of the present invention includes a high bandwidth bus (32) for transmitting data at high bit rates between various video processing subsystem. A graphics processing subsystem (30), having graphics memory, is coupled to the high bandwidth bus (32). The graphics processing subsystem (30) is adapted to receive a video memory and to perform video processing when the video memory is received. The high bandwidth bus (32) is provided with expansion connectors (56, 58) for detachably coupling to various subsystems. These subsystems may include a video processing subsystem (16) and a video capture system. The high bandwidth bus is also provided with a bus bridge (34) for coupling the high bandwidth bus (32) to a low bandwidth bus (42) or a central processing unit bus.

Inventors

  • 👤 Kevin Harney
  • 👤 Louis A. Lippincott

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-10-27 23:48
CPC Classifications
G; G09; G09G; G09G5/00; G09G5/36; G09G5/363; G06; G06F; G06F13/00; G06F13/38; G06F13/42; G06F13/4204; G06F13/4221; G06F13/423; G06F3/00; G06F3/14

Claims Analysis

Total Claims: 7
Claim 1
Independent Claim 104 words
A video processing system comprising: substantially high bandwidth bus means (32) for transmitting data at high bit rates; graphics processing means (30) coupled to said high bandwidth bus means (32) having first graphics memory for performing graphics processing; said graphics processing means (30) having means for detachably receiving and electrically coupling to second video memory, and means for performing video processing when coupled to said second video memory; and said high bandwidth bus means (32) having a plurality of connecting means for detachably receiving a selected subsystem of a plurality of subsystems and electrically coupling said high bandwidth bus means to said selected subsystem.
Claim 2
Dependent Claim 27 words
The video processing system of claim 1, wherein first connecting means (56) of said plurality of connecting means is adapted to receive a video capture subsystem (12).
Claim 3
Dependent Claim 26 words
The video processing system of claim 2, wherein second connecting means (58) of said plurality of connecting means is adapted to receive a video acceleration subsystem.
Claim 4
Dependent Claim 22 words
The video processing system of claim 3, wherein one of said first and second connecting means (56, 58) receives said selected subsystem.
Claim 5
Dependent Claim 22 words
The video processing system of claim 4, wherein each of said first and second connecting means (56, 58) receives a respective subsystem.
Claim 6
Dependent Claim 43 words
The video processing system of claim 1, further comprising: substantially low bandwidth bus means (42); and bus bridge means (34) coupled to said high bandwidth bus (32) and said low bandwidth means (42) for selectably isolating and coupling said bus means (32, 42).
Claim 7
Dependent Claim 24 words
The video processing system of claim 1, including central processing means (38) wherein said central processing means is adapted to perform a software decode.

References Cited (Backward Citations)

No citation records indexed.

USPTO Annuity & Maintenance Windows

Maintenance schedule is calculated for granted US utility patents.

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag