EP0574142A1
Expired / Lapsed
EP
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Driver circuit for dot matrix display apparatus
Assignee: International Business Machines Corp
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Filing: 1993-05-18
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Granted: —
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Expires: 2013-05-18
Abstract
Abstract To expand display data for a low-resolution dot matrix display apparatus to display data for a high-resolution dot matrix display apparatus without causing the reduction of the speed of processing and without requiring clocks of different frequencies, a driver circuit comprises intermediate value generating circuits for generating intermediate values of a plurality of adjacent display data according to the expansion ratio in a driver circuit of a dot matrix display apparatus and by applying also the outputs of the intermediate value generating circuits to a dot matrix display panel, the display data is expanded inside of said driver.
Inventors
- 👤 Atsuhiko Amagami
- 👤 Nobuo Aruga
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-10 02:10
CPC Classifications
G; G09; G09G; G09G3/00; G09G3/20; G09G3/2007; G09G3/34; G09G3/36; G09G3/3611; G09G3/3685; G09G2300/00; G09G2300/08; G09G2300/0809; G09G2300/0842; G09G2300/0857; G09G2310/00; G09G2310/02; G09G2310/0264; G09G2310/0286; G09G2340/00; G09G2340/04; G09G2340/0407; G09G2340/0414; G09G2340/0421; G09G3/2011
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
203 words
A driver circuit (26) for a dot matrix display device (24) having a plurality of signal electrodes (y0, y1,...., yn) and plurality of scanning electrodes (x0, x1,.... xm), in which display pixels are formed at the intersections of the signal electrodes and the scanning electrodes, the driver circuit comprising a shift register (30; 130) for sequentially receiving display data for one display line under the control of a clock signal (CK), the shift register comprising a plurality of first flip-flops (A0, A2, A3, A5; A0, A1, A2, A3) connected in series, and a plurality of second flip-flops (A1, A4; J0,J1, J2), which second flip-flops are connected to at least some of the first flip-flops via intermediate value generating circuits (C0, C1; E0, F0, G0) for generating intermediate values between display data at the input sides and the output sides of the ones of the first plurality of flip-flops to which they are connected, each signal electrode being connected through a line data latch to the output of one of either the first plurality of flip-flops or the second plurality of flip-flops, the line data latches being responsive to line pulses to apply the display data for one display line to the signal electrodes.
Claim 2
Dependent Claim
77 words
A driver circuit as claimed in claim 1 comprising intermediate value generating circuits (D0, D1, D2, D3, D4, D5; S0, M0, S1, M1, S2, M2, S3, M3, S4, S4) arranged between the shift register (30; 130) and the signal electrodes (y0, y1, y2, y3, y4) for generating intermediate values between display data previously output to the signal electrodes and display data newly arranged in the shift register and for applying the intermediate values to the signal electrodes.
Claim 3
Dependent Claim
61 words
A dot matrix display device comprising a plurality of signal electrodes (y0, y1,...., yn) and plurality of scanning electrodes (x0, x1,.... xm), in which display pixels are formed at the intersections of the signal electrodes and the scanning electrodes; a driver circuit as claimed in any preceding claim; and scanning electrode driving means responsive to line pulses to select scanning electrodes.
Claim 4
Independent Claim
77 words
A method for driving a dot matrix display panel having a plurality of signal electrodes and a plurality of scanning electrodes crossing the signal electrodes, on which display dots are formed by the cross points of the signal electrodes and the scanning electrodes; wherein intermediate values for at least part of adjacent display data are generated and applied to said signal electrodes while the display data for one display line are sequentially shifted into a shift register.
Claim 5
Dependent Claim
55 words
The method for driving a dot matrix display panel according to claim 1, wherein when at least part of display lines are driven intermediate values are generated between display data previously outputted to signal electrodes and display data newly arranged in a shift register and the generated intermediate values are applied to said signal electrodes.
Claim 6
Dependent Claim
202 words
A dot matrix display apparatus comprising: a dot matrix display panel having a plurality of signal electrodes and a plurality of scanning electrodes crossing the signal electrodes, on which display dots are formed by the cross points of the signal electrodes and the scanning electrodes, a shift register into which display data are sequentially sent according to pixel clocks until display data for one display line is arranged, a line data latch for applying the display data for one display line sent from the shift register to the signal electrodes according to line pulses, and scanning electrode driving means for selecting scanning electrodes according to line pulses; wherein said register has a plurality of first flip flops connected in series, second flip flop are connected to the output sides of at least part of the first flip flops through intermediate value generating circuits for generating intermediate values between display data on the input sides and display data on the output sides of the first flip flops, the pixel clocks are simultaneously applied to the first and the second flip flops, and a signal electrode is connected, through the line data latch, to each output of the first and the second flip flops.
Claim 7
Dependent Claim
55 words
The dot matrix display apparatus according to claim 7, wherein provided between said shift register and signal electrodes are intermediate value generating circuits for generating intermediate values between display data previously outputted to the signal electrodes and display data newly arranged in the shift register and for applying the intermediate values to the signal electrodes.
Claim 8
Dependent Claim
180 words
An information processing system comprising: an CPU for performing arithmetic operations, a system memory for storing a program executed by the CPU and data used at the run time of the program, a dot matrix display apparatus having a dot matrix display panel and a circuit for driving said panel, a display controller for sending control signals and display data to said driver circuit, and a video buffer memory which holds display data for a display apparatus whose resolution is relatively lower than that of said dot matrix display panel and which is accessible from the CPU and the display controller; wherein said driver circuit has a shift register into which display data are sequentially sent according to pixel clocks until display data for one display line is arranged, and the shift register has a plurality of first flip flops for sequentially shifting said display data sent from the display controller, intermediate value generating circuits for generating intermediate values for at least part of said adjacent display data, and second flip flops for applying said intermediate values to signal electrodes.
References Cited (Backward Citations)
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