US4771279A
Expired / Lapsed
US
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Dual clock shift register
Assignee: Microsoft Technology Licensing LLC
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Filing: 1987-07-10
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Granted: 1988-09-13
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Expires: 2007-07-10
Abstract
Abstract YA dual clock shift register for use in a computer display system for converting a higher resolution image for a computer screen to a lower resolution image for display on a lower resolution display apparatus. The dual clock shift register includes a first shift register which is used to apportion a second shift register between control by two different clock rates.
Inventors
- 👤 Marc R. Hannah
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 13:47
CPC Classifications
G; G09; G09G; G09G5/00; G09G5/36; G09G5/39; G09G5/391
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
464 words
A dual clock shift register comprising: a first shift register having a first register and a second register, said first and said second registers each for storing one of two logical states comprising a first logical state and a second logical state and each of said first and said second registers having an output and a clock signal input, said clock signal inputs being coupled to receive a second clock rate, said output of said first register being coupled to an input of said second register, said first register having a data input coupled to a signal set at said first logical state, and said first register and said second register having a clear signal input for receiving a clear signal to store said second logical state in said first and said second registers; a pair of multiplexers comprising a first multiplexer and a second multiplexer, said first and said second multiplexer each having a first multiplexer input and a second multiplexer input, said first multiplexer input for receiving a signal corresponding to a first clock rate and said second multiplexer input for receiving a signal corresponding to said second clock rate, each of said first and said second multiplexers having a select line, the select line of said first multiplexer being coupled to the output of said first register and the select line of said second multiplexer being coupled to the output of said second register, said first multiplexer having an output and said second multiplexer having an output, wherein the output of said first multiplexer depends on the logical value on said select line of said first multiplexer and the output of said second multiplexer depends on the logical value on said select line of said second multiplexer, the output of said first multiplexer being one of the signal corresponding to the first clock rate and the signal corresponding to the second clock rate; a second shift register having a third register and a fourth register, said third register having a first clock input, said fourth register having a second clock input, said first clock input being coupled to the output of said first multiplexer, said second clock input being coupled to the output of said second multiplexer, said third register having an input and an output, said fourth register having an input and an output, said output of said third register being coupled to said input of said fourth register, wherein the logical state of the output of said first register determines the state of the first clock input of said third register and the logical state of the output of said second register determines the state of the second clock input of said fourth register, whereby said third register may be clocked at a different rate than said fourth register.
Claim 2
Dependent Claim
464 words
A dual clock shift register comprising: a first shift register having a first register and a second register, said first and said second registers each for storing one of two logical states comprising a first logical state and a second logical state and each of said first and said second registers having an output and a clock signal input, said clock signal inputs being coupled to receive a second clock rate, said output of said first register being coupled to an input of said second register, said first register having a data input coupled to a signal set at said first logical state, and said first register and said second register having a clear signal input for receiving a clear signal to store said second logical state in said first and said second registers; a pair of multiplexers comprising a first multiplexer and a second multiplexer, said first and said second multiplexer each having a first multiplexer input and a second multiplexer input, said first multiplexer input for receiving a signal corresponding to a first clock rate and said second multiplexer input for receiving a signal corresponding to said second clock rate, each of said first and said second multiplexers having a select line, the select line of said first multiplexer being coupled to the output of said first register and the select line of said second multiplexer being coupled to the output of said second register, said first multiplexer having an output and said second multiplexer having an output, wherein the output of said first multiplexer depends on the logical value on said select line of said first multiplexer and the output of said second multiplexer depends on the logical value on said select line of said second multiplexer, the output of said first multiplexer being one of the signal corresponding to the first clock rate and the signal corresponding to the second clock rate; a second shift register having a third register and a fourth register, said third register having a first clock input, said fourth register having a second clock input, said first clock input being coupled to the output of said first multiplexer, said second clock input being coupled to the output of said second multiplexer, said third register having an input and an output, said fourth register having an input and an output, said output of said third register being coupled to said input of said fourth register, wherein the logical state of the output of said first register determines the state of the first clock input of said third register and the logical state of the output of said second register determines the state of the second clock input of said fourth register, whereby said third register may be clocked at a different rate than said fourth register.
Claim 3
Dependent Claim
58 words
A dual clock shift register as in claim 1 wherein said dual clock shift register is coupled to a system for converting a high resolution image for a computer screen to a lower resolution image for display on a lower resolution display apparatus, wherein said dual clock shift register is used in said system for storing pixel values.
Claim 4
Dependent Claim
26 words
A dual clock shift register as in claim 2 wherein said dual clock shift register is used for storing pixel values of said lower resolution image.
Claim 5
Dependent Claim
23 words
A dual clock shift register as in claim 2 wherein said dual clock shift register is coupled to said lower resolution display apparatus.
Claim 6
Dependent Claim
48 words
A dual clock shift register as in claim 2 wherein said first clock rate is the clock rate for input sampling of pixel values from said high resolution image and said second clock rate is for the output rate of pixel values to said lower resolution display apparatus.
Claim 7
Dependent Claim
412 words
A dual clock shift register for use in a computer display system for converting a high resolution image for a computer screen to a lower resolution image for display on a lower resolution display apparatus, said computer display system having a first clock rate for inputting data to said computer display system and a second clock rate for outputting data from said computer display system, said dual clock shift register comprising: a first shift register having n registers each for storing one of two logical states comprising a first logical state and a second logical state, each of said n registers having an output, said first shift register having a data input and a clock signal input, said clock signal input being coupled to receive said second clock rate, said data input being coupled to a signal set at said first logical state and said first shift register having a clear signal input for receiving a clear signal to set all n registers to said second logical state; n multiplexers each being associated with a corresponding one of said n registers and having a select line coupled to the output of the corresponding one of said n registers of said first shift register, said n multiplexers each having a first multiplexer input and a second multiplexer input, said first multiplexer input for receiving a signal corresponding to said first clock rate and said second multiplexer input for receiving a signal corresponding to said second clock rate, each of said n multiplexers having an output and being associated with a corresponding one of said n registers of said first shift registers such that the output of one of said n registers of said first shift register is coupled to the select line of the corresponding multiplexer, the logical value on said select line determining the output of said corresponding multiplexer, said output of said corresponding multiplexer being one of the signal corresponding to the first clock rate and the signal corresponding to the second clock rate; a second shift register having m registers, where m=n, each of said m registers being associated with a corresponding one of said n multiplexers, said m registers of said second shift register each having a clock input, each of said clock inputs of said m registers of said second shift register being coupled to a corresponding one of the outputs of said n multiplexers, whereby said second shift register can be clocked at two different clock rates.
Claim 8
Dependent Claim
412 words
A dual clock shift register for use in a computer display system for converting a high resolution image for a computer screen to a lower resolution image for display on a lower resolution display apparatus, said computer display system having a first clock rate for inputting data to said computer display system and a second clock rate for outputting data from said computer display system, said dual clock shift register comprising: a first shift register having n registers each for storing one of two logical states comprising a first logical state and a second logical state, each of said n registers having an output, said first shift register having a data input and a clock signal input, said clock signal input being coupled to receive said second clock rate, said data input being coupled to a signal set at said first logical state and said first shift register having a clear signal input for receiving a clear signal to set all n registers to said second logical state; n multiplexers each being associated with a corresponding one of said n registers and having a select line coupled to the output of the corresponding one of said n registers of said first shift register, said n multiplexers each having a first multiplexer input and a second multiplexer input, said first multiplexer input for receiving a signal corresponding to said first clock rate and said second multiplexer input for receiving a signal corresponding to said second clock rate, each of said n multiplexers having an output and being associated with a corresponding one of said n registers of said first shift registers such that the output of one of said n registers of said first shift register is coupled to the select line of the corresponding multiplexer, the logical value on said select line determining the output of said corresponding multiplexer, said output of said corresponding multiplexer being one of the signal corresponding to the first clock rate and the signal corresponding to the second clock rate; a second shift register having m registers, where m=n, each of said m registers being associated with a corresponding one of said n multiplexers, said m registers of said second shift register each having a clock input, each of said clock inputs of said m registers of said second shift register being coupled to a corresponding one of the outputs of said n multiplexers, whereby said second shift register can be clocked at two different clock rates.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-09-13 | 1992-03-14 | 1992-09-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-09-13 | 1996-03-14 | 1996-09-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-09-13 | 2000-03-14 | 2000-09-13 | $7700.00 | Window Closed / Lapsed |