Patent EP0573170A1 successfully refreshed from Google Patents.
EP0573170A1
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High density EEPROM cell array with novel programming scheme and method of manufacture
Assignee: National Semiconductor Corp
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Filing: 1993-05-18
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Granted: —
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Expires: 2013-05-18
Abstract
Abstract A high density, electrically-erasable programmable read only memory (EEPROM) cell is fabricated by first forming first and second first field oxide (FOX1) regions in a P-well to define a P-type active device region therebetween. Next, first and second N+ buried bit lines are formed in the P-well adjacent to the first and second FOX1 regions, respectively, such that the N+ bit lines define a P-type channel region therebetween. First and second second field oxide (FOX2) regions are then formed adjacent to the FOX1 regions, respectively, and overlying the N+ bit lines, respectively. A layer of gate oxide about 300-500Å thick is then formed on the P-well between the FOX2 regions. A window of tunnel oxide about 80-100Å thick is then defined in the gate oxide. A layer of polysilicon is then formed over the gate oxide, extending into the tunnel window over the tunnel oxide, to define the cell's floating gate. An ONO layer is then formed over the floating gate. Finally, a second layer of polysilicon/tungsten silicide is formed over the ONO to define the cell's control gate. The above-described EEPROM cell is programmed by holding the control gate of the cell at a programming voltage, holding the bit lines at a low supply voltage, and grounding the P-well. While maintaining these conditions, the word line of adjacent EEPROM cells sharing the first and second bit lines are also grounded. The first and second bit lines of adjacent cells sharing the same control line are held at the programming voltage. The cell is erased by holding its control gate at a low supply voltage, holding the bit lines at a programming voltage, and holding the P-well at the programming voltage. While the above-mentioned conditions are maintained, the bit lines of adjacent EEPROM cells sharing the same word line are held at the programming voltage. Furthermore, the word line of adjacent cells sharing the first and second bit lines are held at the programming voltage.
Inventors
- 👤 Albert Bergemont
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 09:26
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/10; H; H10; H10B; H10B41/00; H10B41/30; G11C16/14; H10B69/00; H10D; H10D30/00; H10D30/60; H10D30/68; H10D30/681; H10D30/683; Y; Y10; Y10S; Y10S438/00; Y10S438/972
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
235 words
A method of fabricating an electrically-erasable programmable read only memory (EEPROM) cell in semiconductor material of P-type conductivity, the method comprising: (a) forming first and second spaced-apart first field oxide (FOX1) regions in the P-type semiconductor material to define a P-type active device region therebetween; (b) forming first and second spaced-apart bit lines of N-type conductivity in the P-type semiconductor material adjacent to the first and second FOX1 regions, respectively, such that the first and second bit lines define a P-type channel region therebetween; (c) forming first and second spaced-apart second field oxide (FOX2) regions adjacent to the first and second FOX1 regions, respectively; and overlying the first and second bit lines, respectively; (d) forming a layer of gate dielectric material on the P-type semiconductor material between the first and second FOX2 regions; (e) defining a window of tunnel dielectric material in the gate dielectric material such that the thickness of the tunnel dielectric material is less than the thickness of the gate dielectric material; (f) forming a layer of first conductive material over the gate dielectric material, and extending into the tunnel window over the tunnel dielectric material, to define a floating gate of the EEPROM cell; (g) forming a layer of intermediate dielectric material over the floating gate; and (h) forming a layer of second conductive material over the layer of intermediate dielectric material to define a control gate of the EEPROM cell.
Claim 2
Dependent Claim
24 words
A method as in claim 1 wherein the layer of first conductive material is formed to extend continuously over the entire P-type channel region.
Claim 3
Dependent Claim
65 words
A method as in claim 1 wherein the layer of first conductive material is formed to extend over only a first portion of the P-type channel region such that the layer of second conductive material is formed directly on the gate dielectric material overlying a second portion of the channel region to thereby define the gate of an internal access transistor of the ELPROM cell.
Claim 4
Dependent Claim
19 words
A method as in claim 1 wherein the gate dielectric material and the tunnel dielectric material comprise silicon dioxide.
Claim 5
Dependent Claim
13 words
A method as in claim 4 wherein the first conductive material comprises polysilicon.
Claim 6
Dependent Claim
15 words
A method as in claim 5 wherein the intermediate dielectric material comprises an oxide/nitride/oxide composite.
Claim 7
Dependent Claim
13 words
A method as in claim 6 wherein the second conductive material comprises polysilicon.
Claim 8
Dependent Claim
17 words
A method as in claim 6 wherein the second conductive material comprises polysilicon and overlying tungsten silicide.
Claim 9
Dependent Claim
25 words
A method as in claim 1 wherein the P-type semiconductor material comprises a well of P-type conductivity formed in a silicon substrate of N-type conductivity.
Claim 10
Dependent Claim
228 words
An electriclaly-erasable programmable read only memory (EEPROM) cell formed in semiconductor material of P-type conductivity, the EEPROM cell comprising: (a) first and second spaced-apart first field oxide (FOX1) regions formed in the P-type semiconductor material to define a P-type active device region therebetween; (b) first and second space-apart bit lines of N-type conductivity formed in the P-type semiconductor material adjacent to the first and second FOX1 regions respectively, such that the first and second bit lines define a P-type channel region therebetween; (c) first and second spaced-apart second field oxide (FOX2) regions formed adjacent to the first and second FOX1 regions, respectively, and overlying the first and second bit lines, respectively; (d) a layer of gate dielectric material formed on the P-type semiconductor material between the first and second FOX2 regions and having a window of tunnel dielectric material formed therein such that the thickness of the tunnel dielectric material is less than the thickness of the gate dielectric material; (e) a layer of first conductive material formed over the gate dielectric material, and extending into the tunnel window over the tunnel dielectric material, to define a floating gate of the EEPROM cell; (f) a layer of intermediate dielectric material formed over the floating gate; and (g) a layer of second conductive material formed over the intermediate dielectric material to define a control gate of the EEPROM cell.
Claim 11
Dependent Claim
22 words
An EEPROM cell as in claim 10 wherein the layer of first conductive material extends continuously over the entire P-type channel region.
Claim 12
Dependent Claim
59 words
An EEPROM as in claim 10 wherein the layer of first conductive material extends over only a first portion of the P-type channel region such that the layer of second conductive material is formed directly on the gate dielectric material overlying a second portion of the channel region to thereby define an internal access gate of the EEPROM cell.
Claim 13
Dependent Claim
20 words
An EEPROM cell as in claim 12 wherein the gate dielectric material and the tunnel dielectric material comprise silicon dioxide.
Claim 14
Dependent Claim
14 words
An EEPROM cell as in claim 13 wherein the first conductive material comprises polysilicon.
Claim 15
Dependent Claim
15 words
An EEPROM cell as in claim 14 wherein the intermediate dielectric material comprises oxide/nitride/oxide composite.
Claim 16
Dependent Claim
14 words
An EEPROM cell as in claim 15 wherein the second conductive material comprises polysilicon.
Claim 17
Dependent Claim
18 words
An EEPROM cell as in claim 15 wherein the second conductive material comprises polysilicon and overlying tungsten silicide.
Claim 18
Dependent Claim
26 words
AN EEPROM cell as in claim 10 wherein the P-type semiconductor material comprises a well of P-type conductivity formed in a silicon substrate of N-type conductivity.
Claim 19
Dependent Claim
124 words
A method of programming the electrically- erasable read only memory (EEPROM) cell recited in claim 10, the method comprising: (a) holding the control gate of the EEPROM cell at a programming voltage; (b) holding the first and second bit lines at a low supply voltage; (c) holding the P-type semiconductor material at the low supply voltage; (d) while maintaining the conditions set forth in steps (a) - (c) above, holding the control gate of adjacent EEPROM cells sharing the first and second bit lines at the low supply voltage; and (e) while maintaining the conditions set forth in steps (a) - (d) above, holding the first and second bit lines of adjacent EEPROM cells sharing the same control gate line at the programming voltage.
Claim 20
Dependent Claim
123 words
A method of erasing the electrically-erasable read only memory (EEPROM) cell recited in claim 10, the method comprising: (a) holding the control gate of the EEPROM cell at a low supply voltage; (b) holding the first and second bit lines of the EEPROM cell at a programming voltage; (c) holding the P-type semiconductor material at the programming voltage; (d) while maintaining the conditions set forth in steps (a) - (c), holding the first and second bit lines of adjacent EEPROM cells sharing the same control gate line at the programming voltage; and (e) while maintaining the conditions set forth in steps (a) - (d), holding the control gate of adjacent EEPROM cells sharing the first and second bit lines at the programming voltage.
References Cited (Backward Citations)
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