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Patent EP0569856A2 successfully refreshed from Google Patents.
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EP0569856A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

A/D Converter

Assignee: Yozan Inc
•
Filing: 1993-05-06
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Granted: —
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Expires: 2013-05-06
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Abstract

Abstract The present invention has an object to provide an A/D converter realized by a small size circuit. An A/D converter of this invention for generating a discrete output voltage with a plurality of levels in response to an input analog voltage comprises i) a plurality of FETs each of which corresponds to the level of the output voltage, each the FET having a plurality of gates for receiving outputs of the FETs levels upper than the FET, the input voltage and an offset voltage of negative value; ii) a voltage divider for generating the offset voltage of each the FET; iii) a plurality of inverters corresponding to each the FET for outputting a constant positive voltage in response to a negative output of the corresponding FET and for outputting a zero voltage in response to a positive output voltage of the corresponding FET.

Inventors

  • 👤 Makoto Yamamoto

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-11-09 19:38
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/12; H03M1/34; H03M1/38; H03M1/42; H02; H02M; H02M1/00; H02M1/08; H03M1/36

Claims Analysis

Total Claims: 1
Claim 1
Independent Claim 123 words
An A/D converter for generating a discrete output voltage with a plurality of levels in response to an input analog voltage comprising: i) a plurality of FETs each of which corresponds to said level of said output voltage, each said FET having a plurality of gates for receiving outputs of said FETs levels upper than said FET, said input voltage and an offset voltage of negative value; ii) a voltage divider for generating said offset voltage of each said FET; iii) a plurality of inverters corresponding to each said FET for outputting a constant positive voltage in response to a negative output of said corresponding FET and for outputting a zero voltage in response to a positive output voltage of said corresponding FET.

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