Patent EP0568197A2 successfully refreshed from Google Patents.
EP0568197A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Biomedical amplifier circuit
Assignee: HP Inc
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Filing: 1993-03-31
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Granted: —
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Expires: 2013-03-31
Abstract
Abstract In a mixed analog and digital integrated circuit for physiological signal instrumentation such as electrocardiographs, electromyographs, and electroencephalographs, an electronic differential amplifier comprises a chopper-stabilised first stage amplifier (402, 408, 412), a second stage amplifier (414) providing a negative output (418) and a positive output (416) to a chopper-stabilised feedback circuit (434-444), and a gain feedback circuit (420) which receives the negative output (418) and supplies a gain feedback voltage (24) to the first stage amplifier. The integrated circuit has five signal channels, each with analog amplification and analog to digital conversion. The channels can be configured for various combinations of input signal amplification, input signal summation, analog output driving, and AC impedance measurement. The integrated circuit has two digital serial input lines and two digital serial output lines, all designed for direct connection to optical couplers. Channel configuration, gain, and other parameters are externally controllable by a serial digital input signal. Up to six compatible devices can be serially connected in a chain.
Inventors
- 👤 Richard A. Baumgartner
- 👤 Charles E. Moore
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-05 08:48
CPC Classifications
A; A61; A61B; A61B5/00; A61B5/24; A61B5/30; A61B5/305; A61B5/307; A61B5/308; A61B5/72; A61B5/7203; H; H03; H03F; H03F3/00; H03F3/45; H03F3/45071; H03F3/45076; H03F3/45179; H03F3/45183; H03F3/45188; H03F3/45475; H03F3/45479; H03F3/45632; H03F3/45636; H03F3/45641; H03F3/4565; H03F3/45659; H03F3/45744; H03F3/45775; H03F3/45928; H03F3/45932; H03F3/45937; H03F3/45941; H03F3/45968; H03F3/45973; H03F3/45991; H03F3/45995; A61B5/7235; A61B5/7242; H03F2200/00; H03F2200/261; H03F2200/331; H03F2203/00; H03F2203/45; H03F2203/45644
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
218 words
An electronic differential amplifier circuit prising; first stage amplifier means (402, 408, 412) for receiving an input voltage (400) and a gain feedback voltage (424) and for generating a pair of first stage outputs by differentially amplifying said input voltage and said gain feedback voltage; wherein said first stage amplifier means is chopper stabilized (402, 412); and second stage amplifier means (414) for receiving said pair of first stage outputs and for generating a pair of second stage outputs (416, 418) by differentially amplifying said pair of first stage outputs; wherein said pair of second stage outputs further comprise a negative gain second stage output (418) and a positive gain second stage output (416); and second stage common mode feedback means (434, 438, 440, 442, 444) for receiving said pair of second stage outputs (416, 418) and for generating an average voltage (436) by summing said pair of second stage outputs and for generating a second stage common mode feedback voltage by differentially amplifying said average voltage and a ground voltage; wherein said second stage common mode feedback means is chopper stabilized (438, 442); and gain feedback means (420) for receiving said negative gain second stage output (418) and for generating said gain feedback voltage (424) by forming a fraction of said negative gain second stage output (418).
Claim 2
Dependent Claim
500 words
An electronic differential amplifier circuit comprising: first chopper means (402) for receiving an input voltage (400) and a gain feedback voltage (424) and for generating a pair of first chopper outputs (404, 405) by chopping said input voltage (400) and said gain feedback voltage (424); and first stage signal amplifier means (408) for receiving said pair of first chopper outputs (404, 405) and for generating a pair of first stage outputs (406, 407) by differentially amplifying said pair of first chopper outputs (404, 405); wherein said first stage signal amplifier means (408) has a first stage common bias current; and first stage common mode feedback amplifier means (410) for receiving said pair of first stage outputs (406, 407) and a first reference voltage and for generating a first average by summing said pair of first stage outputs and for generating a first stage common mode bias feedback voltage (548) by differentially amplifying said first average and said first reference voltage; wherein said first stage common mode bias feedback voltage (548) controls said first stage common bias current; and second chopper means (412) for receiving said pair of first stage outputs (406, 407) and for generating a pair of second chopper outputs by chopping said pair of first stage outputs; wherein said second chopper means is synchronous with said first chopper means; and second stage signal amplifier means (414) for receiving said pair of second chopper outputs and for generating a pair of second stage outputs (416, 418) by differentially amplifying said pair of second chopper outputs; wherein said pair of second stage outputs further comprise a negative gain second stage output (418) and a positive gain second stage output (416); and wherein said second stage signal amplifier means has a pair of variable output loads (658, 660); and third chopper means (434, 438) for receiving said second stage outputs (416, 418) and a ground voltage and for generating a second average (436) by summing said pair of second stage outputs and for generating a pair of third chopper outputs by chopping said second average and said ground voltage; and second stage common mode feedback amplifier means (440) receiving said pair of third chopper outputs and for generating a pair of second stage common mode feedback voltages by differentially amplifying said pair of third chopper outputs; and fourth chopper means (442) for receiving said pair of second stage common mode feedback voltages and for generating a pair of fourth chopper outputs by chopping said pair of second stage common mode feedback voltages; and current mirror means (444) for receiving said pair of fourth chopper outputs and for converting said pair of fourth chopper outputs to a second stage load control voltage; wherein said second stage load control voltage controls said pair of variable output loads (658, 660); and gain feedback means (420) for receiving said negative gain second stage output (418) and for generating said gain feedback voltage (424) by forming a fraction of said negative gain second stage output (418).
References Cited (Backward Citations)
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