Patent EP0567355A2 successfully refreshed from Google Patents.
EP0567355A2
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A method and apparatus for operating a multiprocessor computer system having cache memories
Assignee: Compaq Computer Corp
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Filing: 1993-04-26
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Granted: —
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Expires: 2013-04-26
Abstract
Abstract A method for operating a multiprocessor computer system (10) which includes cache memories (204, 210, 226) is provided. A system bus interface (232) initiates a bus write broadcast when a processor (202) writes to the cache memory, sets a SHARED indicator for the data item, monitors the write broadcast for a SHARED signal assertion on the bus, and clears the indicator in the absence of the SHARED signal assertion during the write broadcast. Backup cache memory(226) entry update versus invalidate decisions are made based upon the identity of write broadcast initiators. Cache memories have indexes which are a function of the cache size. A high speed multiplexer (262) selectively couples cache index information from each processor and bus interface to the backup cache memory. A lock register (254) helps synchronize processors.
Inventors
- 👤 Nitin Godiwala
- 👤 Barry A. Maskas
- 👤 Jeffrey A. Metzger
- 👤 Kurt M. Thaller
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-05 11:04
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0806; G06F12/0815; G06F12/0831; G06F12/0833
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
278 words
A method for operating a multiprocessor computer system (10) having a plurality of processors (202), main memory (18,20,22,24) storing a plurality of data items, a bus (28) coupling the processors and main memory to one another, each processor having a bus interface (232) and cache memories which include internal cache memories (204,210) and backup cache memory (226), comprising the steps of: a) making backup cache memory entry update versus invalidate decisions based upon the identity of initiators of write broadcasts; b) having the bus interface: (i) initiate a bus write broadcast when its processor writes a data item in a cache memory, (ii) set a SHARED indicator for the data item, (iii) monitor the write broadcast for assertion of a SHARED signal on the bus, and (iv) cause the SHARED indicator of the data item to be cleared in the absence of an assertion of the SHARED signal on the bus during the write broadcast; c) having cache memories whose indexes are a function of the size of the respective cache memory; d) providing a high speed multiplexer(262) to selectively couple cache index information from each processor and bus interface to the backup cache memory and controlling the multiplexer to select either the cache index supplied by the processor or the cache index supplied by the interface for input to the backup cache memory; and e) synchronizing performance of common tasks among the processors by using a lock register(254) arrangement located at the bus interface of each processor such that LOAD-LOCK and STORE-CONDITIONAL commands synchronize atomic operations performed on a data item stored at a particular location identified by a main memory address specified by a particular processor.
Claim 2
Independent Claim
278 words
A method for operating a multiprocessor computer system (10) having a plurality of processors (202), main memory (18,20,22,24) storing a plurality of data items, a bus (28) coupling the processors and main memory to one another, each processor having a bus interface (232) and cache memories which include internal cache memories (204,210) and backup cache memory (226), comprising the steps of: a) making backup cache memory entry update versus invalidate decisions based upon the identity of initiators of write broadcasts; b) having the bus interface: (i) initiate a bus write broadcast when its processor writes a data item in a cache memory, (ii) set a SHARED indicator for the data item, (iii) monitor the write broadcast for assertion of a SHARED signal on the bus, and (iv) cause the SHARED indicator of the data item to be cleared in the absence of an assertion of the SHARED signal on the bus during the write broadcast; c) having cache memories whose indexes are a function of the size of the respective cache memory; d) providing a high speed multiplexer(262) to selectively couple cache index information from each processor and bus interface to the backup cache memory and controlling the multiplexer to select either the cache index supplied by the processor or the cache index supplied by the interface for input to the backup cache memory; and e) synchronizing performance of common tasks among the processors by using a lock register(254) arrangement located at the bus interface of each processor such that LOAD-LOCK and STORE-CONDITIONAL commands synchronize atomic operations performed on a data item stored at a particular location identified by a main memory address specified by a particular processor.
Claim 3
Dependent Claim
264 words
A computer apparatus for use in a multiprocessor computer system (10) having a main memory (18, 20, 22, 24) storing a plurality of data items and being coupled to a bus (28), the bus being operated according to a SNOOPY protocol, the computer apparatus comprising: a processor (202); a cache memory (226) coupled to the processor and containing a subset of the data items stored in the main memory, for access by the processor; the cache memory including a TAG store comprising a plurality of VALID indicators, one VALID indicator for each of the data items currently contained in the cache memory; and a bus interface (232) coupled to the cache memory and adapted for coupling to the bus, the interface operating according to the SNOOPY protocol to monitor transactions on the bus for write transactions affecting data items of the subset having set VALID indicators; the interface operating to determine the identity of each initiator of a write transaction on the bus affecting a VALID data item of the subset; the interface further operating to invalidate or update each VALID data item of the subset when there is a write transaction affecting the data item, an invalidate operation including a clearing of the corresponding VALID indicator for the affected data item by the interface and an update operation including the overwriting of the affected data item by the interface from the write transaction on the bus, wherein the operation of the interface to invalidate or update is a function of the identity of the initiator of the write transaction determined by the interface.
Claim 4
Dependent Claim
264 words
A computer apparatus for use in a multiprocessor computer system (10) having a main memory (18, 20, 22, 24) storing a plurality of data items and being coupled to a bus (28), the bus being operated according to a SNOOPY protocol, the computer apparatus comprising: a processor (202); a cache memory (226) coupled to the processor and containing a subset of the data items stored in the main memory, for access by the processor; the cache memory including a TAG store comprising a plurality of VALID indicators, one VALID indicator for each of the data items currently contained in the cache memory; and a bus interface (232) coupled to the cache memory and adapted for coupling to the bus, the interface operating according to the SNOOPY protocol to monitor transactions on the bus for write transactions affecting data items of the subset having set VALID indicators; the interface operating to determine the identity of each initiator of a write transaction on the bus affecting a VALID data item of the subset; the interface further operating to invalidate or update each VALID data item of the subset when there is a write transaction affecting the data item, an invalidate operation including a clearing of the corresponding VALID indicator for the affected data item by the interface and an update operation including the overwriting of the affected data item by the interface from the write transaction on the bus, wherein the operation of the interface to invalidate or update is a function of the identity of the initiator of the write transaction determined by the interface.
Claim 5
Dependent Claim
55 words
The computer apparatus of claim 2, wherein the interface performs a first set of invalidate or update operations in respect of write transactions when the identified initiators of write transactions are processors of data and performs a second set of invalidate or update operations when the identified initiators of write transactions are movers of data.
Claim 6
Dependent Claim
24 words
The computer apparatus of claim 1, wherein the interface invalidates or updates affected data items as a function of operating characteristics of the processor.
Claim 7
Dependent Claim
197 words
A computer apparatus for use in a multiprocessor computer system (10) having a main memory (18, 20, 22, 24) storing a plurality of data items and being coupled to a bus (28), the bus being operated according to a SNOOPY protocol, the computer apparatus comprising: a processor (202); a cache memory (204, 210, 226)coupIed to the processor and containing a subset of the data items stored in the main memory, for access by the processor; the cache memory including a TAG store comprising a plurality of SHARED indicators, one SHARED indicator for each of the data items currently contained in the cache memory; and a bus interface (232) coupled to the processor and adapted for coupling to the bus, the bus interface initiating a bus write broadcast when the processor writes to a data item in the cache memory and the SHARED indicator for the data item is set; the bus interface monitoring the bus during the write broadcast for assertion of a SHARED signal on the bus and causing the SHARED indicator of the data item to be cleared in the absence of an assertion of the SHARED signal on the bus during the write broadcast.
Claim 8
Dependent Claim
197 words
A computer apparatus for use in a multiprocessor computer system (10) having a main memory (18, 20, 22, 24) storing a plurality of data items and being coupled to a bus (28), the bus being operated according to a SNOOPY protocol, the computer apparatus comprising: a processor (202); a cache memory (204, 210, 226)coupIed to the processor and containing a subset of the data items stored in the main memory, for access by the processor; the cache memory including a TAG store comprising a plurality of SHARED indicators, one SHARED indicator for each of the data items currently contained in the cache memory; and a bus interface (232) coupled to the processor and adapted for coupling to the bus, the bus interface initiating a bus write broadcast when the processor writes to a data item in the cache memory and the SHARED indicator for the data item is set; the bus interface monitoring the bus during the write broadcast for assertion of a SHARED signal on the bus and causing the SHARED indicator of the data item to be cleared in the absence of an assertion of the SHARED signal on the bus during the write broadcast.
Claim 9
Independent Claim
175 words
A method for operating an interface coupling a processor (202) and a cache memory (204, 210, 226) to a bus (28) of a multiprocessor system (10), the multiprocessor system including a main memory (18, 20, 22, 24) coupled to the bus and storing a plurality of data items, the cache memory containing a subset of the data items stored in the main memory, for access by the processor, and the cache memory including a TAG store comprising a plurality of SHARED indicators, one SHARED indicatorforeach of the data items currently contained in the cache memory, the method comprising the steps of: monitoring the bus for detection of a write affecting a data item of the subset in the cache, with the SHARED indicator for the data item being set; operating to invalidate or update a SHARED data item of the subset when there is a write transaction affecting the data item; and asserting a SHARED signal on the bus when the means operating to invalidate or update a SHARED data item updates the data item.
Claim 10
Independent Claim
175 words
A method for operating an interface coupling a processor (202) and a cache memory (204, 210, 226) to a bus (28) of a multiprocessor system (10), the multiprocessor system including a main memory (18, 20, 22, 24) coupled to the bus and storing a plurality of data items, the cache memory containing a subset of the data items stored in the main memory, for access by the processor, and the cache memory including a TAG store comprising a plurality of SHARED indicators, one SHARED indicatorforeach of the data items currently contained in the cache memory, the method comprising the steps of: monitoring the bus for detection of a write affecting a data item of the subset in the cache, with the SHARED indicator for the data item being set; operating to invalidate or update a SHARED data item of the subset when there is a write transaction affecting the data item; and asserting a SHARED signal on the bus when the means operating to invalidate or update a SHARED data item updates the data item.
Claim 11
Independent Claim
174 words
A method for performing exchange transactions between caches (204, 210, 226) and a main memory (18, 20, 22, 24), the caches and main memory being coupled to one another by a bus (28) the method comprising the steps of: providing caches of different sizes including a cache having a smallest size, each cache having an index fixed as a function of the size of the cache; identifying an address field for each exchange transaction; for each exchange transaction, transmitting one of the address field and the exchange address field, identified in respect of the exchange transaction, over the bus from one of the caches related to the exchange transaction to the main memory; for the exchange transaction of the preceding step, transmitting a preselected portion of the other of the address field and the exchange address field over the bus, from the one of the caches to the main memory, the preselected portion comprising the other of the address field and the exchange address field minus the cache index of the smallest size cache.
Claim 12
Independent Claim
174 words
A method for performing exchange transactions between caches (204, 210, 226) and a main memory (18, 20, 22, 24), the caches and main memory being coupled to one another by a bus (28) the method comprising the steps of: providing caches of different sizes including a cache having a smallest size, each cache having an index fixed as a function of the size of the cache; identifying an address field for each exchange transaction; for each exchange transaction, transmitting one of the address field and the exchange address field, identified in respect of the exchange transaction, over the bus from one of the caches related to the exchange transaction to the main memory; for the exchange transaction of the preceding step, transmitting a preselected portion of the other of the address field and the exchange address field over the bus, from the one of the caches to the main memory, the preselected portion comprising the other of the address field and the exchange address field minus the cache index of the smallest size cache.
Claim 13
Dependent Claim
200 words
A computer apparatus, which comprises: a processor (202) a bus interface (232) coupled to the processor and adapted for coupling to a bus; a cache memory (226); and a multiplexer (262) including a first cache index input coupled to the processor and a second cache index input coupled to the bus interface, and a cache index output coupled to the cache memory; the multiplexer selectively coupling the first and second cache index inputs to the cache index output; the bus interface operating to monitor the bus for bus control signal information indicative of the initiation of a bus transaction and being responsive to the bus control signal information to generate and transmit to the processor, a bus transaction signal to alert the processor of an imminent bus transaction; the processor being responsive to the bus transaction signal to gracefully complete or stall a current cache memory access operation, via the coupling of the first cache index input to the cache index ouptput of the multiplexer, within a preselected period of time; the bus interface operating, upon the conclusion of the preselected period of time, to control the multiplexer to couple the second cache index input to the cache index output.
Claim 14
Dependent Claim
200 words
A computer apparatus, which comprises: a processor (202) a bus interface (232) coupled to the processor and adapted for coupling to a bus; a cache memory (226); and a multiplexer (262) including a first cache index input coupled to the processor and a second cache index input coupled to the bus interface, and a cache index output coupled to the cache memory; the multiplexer selectively coupling the first and second cache index inputs to the cache index output; the bus interface operating to monitor the bus for bus control signal information indicative of the initiation of a bus transaction and being responsive to the bus control signal information to generate and transmit to the processor, a bus transaction signal to alert the processor of an imminent bus transaction; the processor being responsive to the bus transaction signal to gracefully complete or stall a current cache memory access operation, via the coupling of the first cache index input to the cache index ouptput of the multiplexer, within a preselected period of time; the bus interface operating, upon the conclusion of the preselected period of time, to control the multiplexer to couple the second cache index input to the cache index output.
Claim 15
Dependent Claim
127 words
The computer apparatus of claim 8, wherein: the cache memory comprises a data store and a TAG store, each including a cache index input; and the cache index ouptut comprises a first cache index output selectively coupling one of the first and second cache index inputs, to the cache index input of the data store and a second cache index output selectively coupling one of the first and second cache index inputs to the cache index input of the TAG store; the interface operating to control the multiplexer to independently couple one of the first and second cache index inputs to the cache input of the data store and one of the first and second cache index inputs to the cache index input of the TAG store.
Claim 16
Dependent Claim
231 words
A lock mechanism for use in a multiprocessor system to synchronize the performance of common tasks, the multiprocessor system comprising a plurality of processors (202) and a main memory (18, 20, 22, 24) coupled to one another by a bus (28), each processor being able to assert LOAD-LOCK and STORE-CONDITIONAL commands, the lock mechanism comprising: an interface unit (232) adapted for coupling to one of the processors of the system and to the bus; and a register device (254) coupled to the interface unit, the register device including a VALID indicator; the interface unit being responsive to the assertion of the LOAD-LOCK command by the corresponding one of the processors to store a main memory address for the LOAD-LOCK command in the register device and to set the VAID indicator; the interface unit operating, after the assertion of the LOAD-LOCK command, to monitor the bus for write transactions affecting the main memory address stored in the register device and to clear the VALID indicator upon the detection of a write transaction affecting the main memory address; the interface unit being responsive to the assertion of the STORE-CONDITIONAL command by the corresponding one of the processors to check the VALID indicator in the register device and to: i) cause the completion of the STORE-CONDITIONAL command when the VALID indicator is set; ii) fail the STORE-CONDITIONAL command when the VALID indicator is cleared.
Claim 17
Dependent Claim
231 words
A lock mechanism for use in a multiprocessor system to synchronize the performance of common tasks, the multiprocessor system comprising a plurality of processors (202) and a main memory (18, 20, 22, 24) coupled to one another by a bus (28), each processor being able to assert LOAD-LOCK and STORE-CONDITIONAL commands, the lock mechanism comprising: an interface unit (232) adapted for coupling to one of the processors of the system and to the bus; and a register device (254) coupled to the interface unit, the register device including a VALID indicator; the interface unit being responsive to the assertion of the LOAD-LOCK command by the corresponding one of the processors to store a main memory address for the LOAD-LOCK command in the register device and to set the VAID indicator; the interface unit operating, after the assertion of the LOAD-LOCK command, to monitor the bus for write transactions affecting the main memory address stored in the register device and to clear the VALID indicator upon the detection of a write transaction affecting the main memory address; the interface unit being responsive to the assertion of the STORE-CONDITIONAL command by the corresponding one of the processors to check the VALID indicator in the register device and to: i) cause the completion of the STORE-CONDITIONAL command when the VALID indicator is set; ii) fail the STORE-CONDITIONAL command when the VALID indicator is cleared.
References Cited (Backward Citations)
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