Patent EP0564191A2 successfully refreshed from Google Patents.
EP0564191A2
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Structure and method for fabricating integrated circuits
Assignee: STMicroelectronics lnc USA
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Filing: 1993-03-26
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Granted: —
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Expires: 2013-03-26
Abstract
Abstract A structure and method is provided for fabricating an integrated circuit having an N-type well and a P-type well, with the upper surfaces of the N-type well and the P-type well coplanar. An insulating layer is formed over the integrated circuit. A first masking layer is formed over the insulating layer to define locations of a first well to be formed. An impurity of a first conductivity type is implanted into the semiconductor substrate of the integrated circuit to form a first region. The first masking layer is removed, and a second masking layer is formed over the insulating layer to define locations of a second well to be formed. An impurity of a second conductivity type is implanted into the semiconductor substrate of the integrated circuit to form a second region. The second masking layer is then removed. The integrated circuit is thermally heated to form the first and second wells in the substrate. If desired, sets of alignment keys may be formed in a semiconductor wafer by first forming a layer of insulating material over a semiconductor wafer, followed by forming a layer of masking material to define the locations of the sets of alignment keys and anisotropically etching into the semiconductor wafer to form the sets of alignment keys. The sets of alignment keys may be formed in a portion of the semiconductor wafer that is not part of a substrate for any particular integrated circuit.
Inventors
- 👤 Frank R. Bryant
- 👤 Tsui C. Chan
- 👤 Kuei-Wu Huang
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-08 23:25
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/0191; H10D84/02; H10D84/03; H10D84/038; H10W; H10W46/00; H10W46/301; H10W46/501
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
112 words
A method for forming an integrated circuit, comprising the steps of: forming an insulating layer over a semiconductor substrate; forming a first masking layer over a portion of the insulating layer to define locations of a first well to be formed in the semiconductor substrate; forming a first region in the semiconductor substrate where the first well will be formed; removing the first masking layer; forming a second masking layer over a portion of the insulating layer to define locations of a second well to be formed in the semiconductor substrate; forming a second region in the semiconductor substrate where the second well will be formed; and removing the second masking layer.
Claim 2
Dependent Claim
61 words
The method of Claim 1, wherein prior to said step of forming the insulating layer the following steps are performed: forming a layer of masking material over a semiconductor wafer to define the locations of sets of alignment keys; etching into a portion of the semiconductor wafer to form the sets of alignment keys; and removing the layer of masking material.
Claim 3
Dependent Claim
25 words
The method of Claim 2, wherein a layer of insulating material is formed on the semiconductor wafer before the layer of masking material is formed.
Claim 4
Dependent Claim
23 words
The method of Claim 1 or 3 wherein said step of forming the insulating layer comprises thermally growing oxide over the semiconductor substrate.
Claim 5
Dependent Claim
26 words
The method of Claim 1, wherein said step of forming the first region comprises implanting an impurity of a first conductivity type into the semiconductor substrate.
Claim 6
Dependent Claim
26 words
The method of Claim 1, wherein said step of forming the second region comprises implanting an impurity of a second conductivity type into the semiconductor substrate.
Claim 7
Independent Claim
188 words
A method for forming an integrated circuit, comprising the steps of: forming a layer of insulating material over a semiconductor wafer; forming a layer of masking material over the layer of insulating material to define the locations of sets of alignment keys; etching into a portion of the semiconductor wafer to form the sets of alignment keys; removing the layer of masking material; forming an insulating layer over the layer of insulating material covering a semiconductor substrate; forming a first masking layer over a portion of the insulating layer to define locations of a first well to be formed in the semiconductor substrate; implanting an impurity of a first conductivity type into the semiconductor substrate to form a first region where the first well will be formed; removing the first masking layer; forming a second masking layer over a portion of the insulating layer to define locations of a second well to be formed in the semiconductor substrate; implanting an impurity of a second conductivity type into the semiconductor substrate to form the second region where the second well will be formed; and removing the second masking layer.
Claim 8
Dependent Claim
23 words
The method of Claim 7 wherein said step of forming the layer of insulating material comprises thermally growing oxide over the semiconductor substrate.
Claim 9
Dependent Claim
34 words
The method of Claim 2 or 7 wherein said step of forming the layer of masking material comprises depositing and patterning a photoresist mask to define the locations of the sets of alignment keys.
Claim 10
Dependent Claim
23 words
The method of Claim 7 wherein said step of etching into a portion of the semiconductor wafer comprises anisotropically etching the semiconductor wafer.
Claim 11
Dependent Claim
28 words
The method of Claim 7 wherein said sets of alignment keys are formed in a portion of the semiconductor wafer which is not part of the integrated circuit.
Claim 12
Dependent Claim
27 words
The method of Claim 7 wherein said step of forming the insulating layer comprises thermally growing oxide over the layer of insulating material covering the semiconductor substrate.
Claim 13
Dependent Claim
37 words
The method of Claim 1 or 7 wherein said step of forming a first masking layer comprises depositing and patterning a photoresist mask to define locations of the first well to be formed in the semiconductor substrate.
Claim 14
Dependent Claim
35 words
The method of Claim 13 wherein the photoresist mask is aligned with the sets of alignment keys before it is patterned to define locations of the first well to be formed in the semiconductor substrate.
Claim 15
Dependent Claim
31 words
The method of Claim 7 wherein said step of implanting the impurity of the first conductivity type comprises implanting an N-type impurity into the semiconductor substrate to form the first region.
Claim 16
Dependent Claim
37 words
The method of Claim 1 or 7 wherein said step of forming the second masking layer comprises depositing and patterning a photoresist mask to define locations of the second well to be formed in the semiconductor substrate.
Claim 17
Dependent Claim
37 words
The method of Claim 16 wherein the photoresist mask is aligned with the sets of alignment keys before the photoresist mask is patterned to define locations of the second well to be formed in the semiconductor substrate.
Claim 18
Dependent Claim
30 words
The method of Claim 7 wherein said step of implanting the impurity of the second conductivity type comprises implanting a P-type impurity into the substrate to form the second region.
Claim 19
Dependent Claim
27 words
The method of Claim 1 or 7 further comprising the step of thermally heating the integrated circuit to form the first and second wells in the substrate.
Claim 20
Dependent Claim
30 words
The method of Claim 1 or 7 further comprising the step of forming a region of field oxide between and within portions of the first well and the second well.
Claim 21
Dependent Claim
32 words
A structure in an integrated circuit, comprising: a N-type well in a semiconductor substrate; a P-type well in the semiconductor substrate, wherein the upper surface of the N-well and P-well are coplanar.
Claim 22
Dependent Claim
16 words
The structure of Claim 21 further comprising sets of alignment keys formed in a semiconductor wafer.
Claim 23
Dependent Claim
28 words
The structure of Claim 22 wherein the sets of alignment keys are formed in a portion of the semiconductor wafer that is not part of the integrated circuit.
Claim 24
Dependent Claim
20 words
The structure of Claim 21 further comprising a region of field oxide between the N-type well and the P-type well.
References Cited (Backward Citations)
No citation records indexed.
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