Patent US106388A successfully refreshed from Google Patents.
Patent EP0562307A2 successfully refreshed from Google Patents.
EP0562307A2
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EP
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Trench EEPROM cell
Assignee: International Business Machines Corp
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Filing: 1993-03-02
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Granted: —
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Expires: 2013-03-02
Abstract
Abstract The objects of the present invention are accomplished by merging a MOSFET device and a floating gate into a three dimensional trench structure. The trench device cell has four vertical sides and bottom. The bottom of the trench forms the channel region (103) of the transfer FET of the EEPROM cell. The heavily doped source and drain regions (47,50) are formed on two vertical sidewalls of the trench (45) and oppositely face each other. The heavily doped regions cover the entire sidewall and have a depth which is greater than the trench depth so that the channel region (103) is defined by the bottom of the trench. The remaining two vertical sidewalls of the trench (45) are formed by isolation oxide (70). A first silicon dioxide layer covers the bottom of the trench (45) and forms part of the gate oxide (105) of the cell device. A second silicon dioxide layer (100) covers the vertical sidewalls of the trench. The second silicon dioxide layer is relatively thin with respect to the gate oxide layer (105). The second silicon dioxide layer (100) separates the source and drain regions (47,50) from the floating gate (110) which overlays both the first and second silicon dioxide layers. The floating gate (110) overlaps all four trench sidewalls and substantially increases the coupling between the floating gate (110) and a control gate (40). The control gate (40) overlies the floating gate (110) and the control gate is separated from the floating gate by a separate dielectric layer (115). The second silicon dioxide layer (100) is relatively thin so that tunneling of electrons between the vertical sidewalls which incorpoate the source and drain regions (47,50) and the floating gate (110) will occur. Tunnelling is the mechanism which charges and discharges the floating gate. The trench EEPROM memory structure occupies a small amount of surface are a while maintaining a high coupling ratio between the control gate (40) and the floating gate (110). The high coupling ratio between the floating gate and the control gate is maintained because the floating gate is butted to isolation oxide on two sides of the trench. The trench EEPROM memory structure of the present invention also reduces program and erase time because the floating gate can be programmed or charged through either the source or drain regions in many cells at one time.
Inventors
- 👤 Alexandre Acovic
- 👤 Ching-Hsiang Hsu
- 👤 Being Song Wu
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-05 21:26
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/10; G11C16/12; G11C16/14; H10B69/00; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0411; H10D30/60; H10D30/68; H10D30/681; H10D30/683
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
165 words
A semiconductor device, comprising: a semiconductor substrate (130) having a major surface, first and second sidewall surfaces, and a channel region (103); said first sidewall surface forming a trench (45) in said substrate with said second sidewall surface and said channel region (103), said first sidewall surface being separated from said second sidewall surface by said channel region (103), said channel region forming a bottom surface of said trench, said first and second sidewall surfaces being generally orthogonal with respect to said substrate major surface; said first and second sidewall surfaces being doped with a first type of dopant; a first dielectric layer (100) overlaying said first and second sidewall surfaces; a second dielectric layer (105) interposed between said channel region (103) and a floating gate (110), said floating gate covers said second dielectric layer (105) and at least partially covers said first dielectric layer (100); and a third dielectric layer (115) interposed between said floating gate layer (110) and a control gate layer (40).
Claim 2
Dependent Claim
165 words
A semiconductor device, comprising: a semiconductor substrate (130) having a major surface, first and second sidewall surfaces, and a channel region (103); said first sidewall surface forming a trench (45) in said substrate with said second sidewall surface and said channel region (103), said first sidewall surface being separated from said second sidewall surface by said channel region (103), said channel region forming a bottom surface of said trench, said first and second sidewall surfaces being generally orthogonal with respect to said substrate major surface; said first and second sidewall surfaces being doped with a first type of dopant; a first dielectric layer (100) overlaying said first and second sidewall surfaces; a second dielectric layer (105) interposed between said channel region (103) and a floating gate (110), said floating gate covers said second dielectric layer (105) and at least partially covers said first dielectric layer (100); and a third dielectric layer (115) interposed between said floating gate layer (110) and a control gate layer (40).
Claim 3
Dependent Claim
43 words
A semiconductor device, as in claim 1, further comprising: isolation material (70) partially filling said trench and forming a first and second isolation sidewall in said trench (45); and said floating gate (110) at least partially covers said first and second isolation sidewalls.
Claim 4
Dependent Claim
37 words
A semiconductor device, as in claim 1 or 2, wherein: said first dielectric layer has a thickness less than said second dielectric layer; and said first dielectric layer has a thickness of less than approximately 15 nm;
Claim 5
Dependent Claim
21 words
A semiconductor device, as in any one of the claims 1 to 3, wherein: said first type of dopant is N-type.
Claim 6
Dependent Claim
21 words
A semiconductor device, as in any one of the claims 1 to 3, wherein: said first type of dopant is P-type.
Claim 7
Dependent Claim
57 words
A semiconductor device, as in any one of the claims 1 to 5, wherein: said floating gate has an interface side and a patterned side, said interface side contacts said first and second dielectric layers, said patterned side has at least two generally planar surfaces for increasing the capacitance between said floating gate and said control gate.
Claim 8
Independent Claim
124 words
A method of making a semiconductor device, comprising: etching a trench in a semiconductor substrate, said trench etching forming first and second trench sidewalls and a channel region, said channel region separates said first trench sidewall from said second trench sidewall; partially filling said trench with isolation material to form first and second isolation sidewalls in said trench, said channel region separates said first isolation sidewall from said second isolation sidewall; doping said first and second trench sidewalls with a first type of dopant; forming a first dielectric layer over said first and second trench sidewalls; forming a second dielectric layer over said channel region; and forming a floating gate covering said second dielectric layer and at least partially covering said first dielectric layer.
Claim 9
Independent Claim
124 words
A method of making a semiconductor device, comprising: etching a trench in a semiconductor substrate, said trench etching forming first and second trench sidewalls and a channel region, said channel region separates said first trench sidewall from said second trench sidewall; partially filling said trench with isolation material to form first and second isolation sidewalls in said trench, said channel region separates said first isolation sidewall from said second isolation sidewall; doping said first and second trench sidewalls with a first type of dopant; forming a first dielectric layer over said first and second trench sidewalls; forming a second dielectric layer over said channel region; and forming a floating gate covering said second dielectric layer and at least partially covering said first dielectric layer.
Claim 10
Dependent Claim
25 words
A method for making a semiconductor device, as in claim 7, wherein: said floating gate at least partially covers said first and second isolation sidewalls.
Claim 11
Dependent Claim
41 words
A method for making a semiconductor device, as in claim 7 or 8, wherein: said first dielectric layer has a thickness less than said second dielectric layer; and said first dielectric layer has a thickness of less than approximately 150 Å;
Claim 12
Independent Claim
25 words
A method for making a semiconductor device, as in any one of the claims 7 to 9, wherein: said first type of dopant is N-type.
Claim 13
Independent Claim
25 words
A method for making a semiconductor device, as in any one of the claims 7 to 9, wherein: said first type of dopant is P-type.
Claim 14
Independent Claim
61 words
A method for making a semiconductor device, as in any one of the claims 7 to 11, wherein: said floating gate has an interface side and a patterned side, said interface side contacts said first and second dielectric layers, said patterned side has at least two generally planar surfaces for increasing the capacitance between said floating gate and said control gate.
Claim 15
Independent Claim
49 words
A method for charging a floating gate in a memory cell, wherein said memory cell comprises a single transistor, a wordline connection, and two bit line connections, comprising: applying a tunnelling voltage to said wordline connection; and applying approximately a ground potential to said bit line connections or vice-versa.
Claim 16
Independent Claim
49 words
A method for charging a floating gate in a memory cell, wherein said memory cell comprises a single transistor, a wordline connection, and two bit line connections, comprising: applying a tunnelling voltage to said wordline connection; and applying approximately a ground potential to said bit line connections or vice-versa.
Claim 17
Independent Claim
79 words
A method for charging a plurality of floating gates in an array of memory cells, wherein each memory cell comprises a single transistor, a wordline connection, and two bit line connections, comprising: applying a tunnelling voltage to a plurality of wordline connections in said array of memory cells wherein said tunnelling voltage is applied to at least 100 memory cells; and applying approximately a ground potential to a plurality of bit line connections in said array of memory cells.
Claim 18
Independent Claim
79 words
A method for charging a plurality of floating gates in an array of memory cells, wherein each memory cell comprises a single transistor, a wordline connection, and two bit line connections, comprising: applying a tunnelling voltage to a plurality of wordline connections in said array of memory cells wherein said tunnelling voltage is applied to at least 100 memory cells; and applying approximately a ground potential to a plurality of bit line connections in said array of memory cells.
Claim 19
Independent Claim
79 words
A method for discharging a plurality of floating gates in an array of memory cells, wherein each memory cell comprises a single transistor, a wordline connection, and two bit line connections, comprising: applying a tunnelling voltage to a plurality of bit line connections in said array of memory cells; and applying approximately a ground potential to a plurality of wordline connections in said array of memory cells wherein said ground potential is applied to at least 100 memory cells.
Claim 20
Independent Claim
79 words
A method for discharging a plurality of floating gates in an array of memory cells, wherein each memory cell comprises a single transistor, a wordline connection, and two bit line connections, comprising: applying a tunnelling voltage to a plurality of bit line connections in said array of memory cells; and applying approximately a ground potential to a plurality of wordline connections in said array of memory cells wherein said ground potential is applied to at least 100 memory cells.
References Cited (Backward Citations)
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