Patent EP0560077A2 successfully refreshed from Google Patents.
EP0560077A2
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EP
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Multichip module substrate and method of manufacture thereof
Assignee: Rogers Corp
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Filing: 1993-02-12
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Granted: —
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Expires: 2013-02-12
Abstract
Abstract In accordance with the present invention, an MCM substrate product is manufactured in an additive process using multiple layers of a fluoropolymer composite material and copper. The copper layers are plated, and the fluoropolymer composite layers are laminated. A seeding process promotes reliable bonding between the fluoropolymer composite material and the plated copper. The use of the filled fluoropolymeric composite eliminates the need for a barrier metal layer between the insulation and the conductors. The MCM substrate device of the present invention may have multiple metal layer and multiple dielectric layers; four or five, or more, of each in a single structure would be easily achieved and is typical. The structure would include lead lines in separate mutually orthogonal planes (sometimes referred to as "x" and "y" lead lines) (84, 67) sandwiched between ground and power voltage planes of copper. The MCM substrate device of the present invention also has solid copper vias (20, 22), which may be used either as electrical interconnection between layers of the MCM substrate and/or to the I/C's to be packaged in the module, or as thermal vias (67, 67a) for heat conduction for thermal management. The manufacturing process of the present invention makes it possible to start or stop any via in any layer of the device. Further in accordance with the present invention, the uppermost layer of the MCM substrate structure (on which the I/C's would be mounted) may be rigidized to improve wire bonding and handling capabilities and characteristics of the MCM substrate structure. The rigidized upper layer is in place of a fluoropolymer layer; and preferably the rigidized upper layer is a cyanate ester/silica layer.
Inventors
- 👤 W. David Smith
- 👤 John A. Olenick
- 👤 Carlos L. Barton
- 👤 Jane L. Cercena
- 👤 Daniel J. Navarro
- 👤 Kathleen R. Olenick
- 👤 Angela M. Kneeland
- 👤 Thomas S. Kneeland
- 👤 Mark F. Sylvester
- 👤 Curtis H. Kempton
- 👤 Scott E. Derosier
- 👤 Lynn E. Burdick
- 👤 Richard T. Traskos
- 👤 Robert B. Huntington
- 👤 James S. Rivers
- 👤 Samuel Gazit
- 👤 Jeffrey B. Otto
- 👤 William P. Harper
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-03 07:28
CPC Classifications
H; H10; H10W; H10W70/00; H10W70/01; H10W70/05; H05; H05K; H05K3/00; H05K3/10; H05K3/20; H05K3/205; H05K3/46; H05K3/4611; H05K3/4614; H05K3/4617; H05K3/4626; H05K3/4632; H05K3/4644; H05K3/4647; H05K3/4682; H10W70/60; H10W70/611; H10W70/67; H10W70/68; H10W70/685; H10W70/69; H05K1/00; H05K1/02; H05K1/0201; H05K1/0203; H05K1/0204; H05K1/0206; H05K1/0286; H05K1/0287; H05K1/0289; H05K2201/00; H05K2201/01; H05K2201/0104; H05K2201/0129; H05K2201/0137; H05K2201/015; H05K2201/09; H05K2201/09209; H05K2201/095; H05K2201/09563; H05K2203/00; H05K2203/07; H05K2203/0703; H05K2203/0726; H05K2203/0733; H05K2203/11; H05K2203/1189; H05K3/22; H05K3/24; H05K3/243; H05K3/28; H05K3/30; H05K3/32; H05K3/328; H05K3/40; H05K3/42; H05K3/423; H05K3/4652; H05K3/4658; H10P; H10P72/00; H10P72/70; H10P72/74; H10P72/7424; Y; Y10; Y10S; Y10S428/00; Y10S428/901; Y10T; Y10T29/00; Y10T29/49; Y10T29/49002; Y10T29/49117; Y10T29/49124; Y10T29/49155; Y10T29/49165
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
477 words
A method of forming a multichip module substrate characterised by the steps of selecting a planar platform (10) having opposed mutually parallel surfaces, forming first via sites (16, 18) on a first (12) of said surfaces of said platform (10), plating in said via sites (16, 18) to form first vias (20a, 22a) in said via sites (16, 18) to define a first subassembly, laminating a first sheet of filled fluoropolymeric composite material (24) onto said first assembly to define a laminated first subassembly, planarizing said laminated first assembly to expose selected ones of said first vias (20a, 22a) and to define a first planarized surface (28), depositing a first thin metallized seed layer (30) on said first planarized surface (28), forming "y" circuit line sites (64) and second via sites (16a, 18a) on said first seed layer, plating "y" circuit lines (67) and second vias (20b, 22b) in said "y" circuit line sites (64) and said second via sites (16a, 18a), respectively, selectively flash etching said first seed layer (30) to define a second subassembly, laminating a second sheet (72) of filled fluoropolymeric composite material onto said second subassembly, planarizing said laminated second subassembly to expose selected ones of said second vias (20, 22, 69, 70) and define a second planarized surface (76), depositing a second thin metallized seed layer (78) on said second planarized surface (76), forming "x" circuit line sites (82) and third via sites (16c, 18c, 17a) on said second seed layer (78), plating "x" circuit lines (84) and third vias (20d, 22d, 69b) in said "x" circuit line sites (82) and said third via sites (16c, 18c, 17a), respectively, selectively flash etching said second seed layer (78) to define a third subassembly, laminating a third sheet of filled fluoropolymeric composite material (88) onto said third subassembly, planarizing said laminated third subassembly to expose selected ones of said third vias and define a third planarized surface (92), depositing a third thin metallized seed layer (94) on said third planarized surface (92), forming voltage plane sites and fourth via sites (16e, 18e, 17c, 85b) on said third seed layer (94), plating a voltage plane (98) on said third seed layer (94) and plating fourth vias (20g, 22g, 69e, 87c) in said fourth via sites (16e, 18e, 17c, 85b), selectively flash etching said third seed layer (94) to define a fourth subassembly, providing a cover layer (108) on said fourth subassembly, planarizing said covered fourth subassembly to expose selected ones of said fourth vias (20g, 22g, 69e, 87c) on a fourth planarized surface, depositing a fourth thin metallized seed layer (104) on said fourth planarized surface, forming pad sites (16f, 18f, 17f, 85c, 99a) on said fourth seed layer (104), plating pads (20b, 22b, 69f, 87d, 101a) in said pad sites (16f, 18f, 17f, 85c, 99a), and selectively flash etching said fourth seed layer (104).
Claim 2
Dependent Claim
15 words
The method of claim 1 characterised in that said planar platform defines a ground plane.
Claim 3
Independent Claim
85 words
The method of claims 1 and 2 characterised in that said steps of forming said first (16, 18), second (16a, 18a), third (16c, 18c, 17a) and fourth (16e, 18e, 17c, 85b) via sites and said steps of forming said "x" and "y" circuit line sites (64, 82) include the steps of selectively depositing photoresist material (62, 66, 80, 86, 100), imaging said deposited photoresist material (62, 66, 80, 86, 100), and developing said imaged photoresist material (62, 66, 80, 86, 100) to define said sites.
Claim 4
Independent Claim
28 words
The method of any of the claims 1, 2 and 3 including the step of removing any undeveloped photoresist between the plating steps and the flash etching steps.
Claim 5
Dependent Claim
47 words
The method of claim 3 characterised in that said steps of plating said first, second, third and fourth vias includes the step of controlling the height of the vias to be equal to or less than the height of the photoresist (14, 62, 66, 80, 86, 100).
Claim 6
Independent Claim
38 words
The method of any of the claims 1 to 5 characterised in that each of said sheets (24, 72, 88) of filled fluoropolymeric composite material includes a thin release layer (26, 74, 90) on a top surface thereof.
Claim 7
Independent Claim
24 words
The method of any of the claims 1 to 6 characterised in that said filled fluoropolymeric composite material comprises silane coated, silica filled polytetrafluoroethylene.
Claim 8
Independent Claim
113 words
The method of any of the claims 1 to 7 characterised in that said laminating steps comprise (a) at a low pressure, ramping of the laminating temperature up to about 370°C (700°F), (b) increasing the pressure to 35 to 117 bar (500 to 1700 p.s.i.), (c) soaking at about 37°C (700°F) and 35 to 117 bar (500 to 1700 p.s.i.), (d) reducing the temperature to about 204° (400°F) while main-taining a pressure of 35 to 117 bar (500 to 1700 p.s.i.), (e) reducing the pressure to about 6,9 bar (100 p.s.i.) while maintaining the temperature of 204° (400°F), (f) cooling to below 37° (100°F) at a pressure of about 6,9 bar (100 p.s.i.)
Claim 9
Independent Claim
21 words
The method of any of the claims 1 to 8 characterised in that said steps of planarizing comprise a flycutting process.
Claim 10
Dependent Claim
22 words
The method of claim 9 characterised in that said flycutting process utilizes a diamond cutting tool operated at a positive rake angle.
Claim 11
Independent Claim
17 words
The method of claims 8 and 9 characterised in that said positive rake angle is about 4°.
Claim 12
Independent Claim
30 words
The method of any of the claims 1 to 11 characterised in that said steps of depositing seed layers (30, 78, 24, 104) comprise sputter coating in an argon gas.
Claim 13
Independent Claim
25 words
The method of any of the claims 1 to 12 characterised in that said cover layer comprises a fourth sheet of filled fluoropolymeric composite material.
Claim 14
Independent Claim
23 words
The method of any of the claims 1 to 13 characterised in that said cover layer (102) comprises a filled cyanate ester resin.
Claim 15
Independent Claim
20 words
The method of any of the claims 1 to 14 characterised in that said pads comprise nickel/gold or solder plating.
Claim 16
Independent Claim
19 words
The method of any of the claims 1 to 15 characterised in that said vias define solid copper plugs.
Claim 17
Independent Claim
22 words
The method of any of the claims 1 to 16 characterised in that at least some of said vias define blind vias.
Claim 18
Independent Claim
30 words
The method of any of the claims 1 to 17 characterised in that at least some of said fourth vias extend through, but are electrically isolated from said voltage plane.
Claim 19
Independent Claim
29 words
The method of any of the claims 1 to 18 characterised in that selected first and second vias (20, 22) are vertically aligned and are electrically and mechanically connected.
Claim 20
Independent Claim
31 words
The method of any of the claims 1 to 19 characterised in that selected first, second and third vias (20, 22, 69) are vertically aligned and are electrically and mechanically connected.
Claim 21
Independent Claim
33 words
The method of any of the claims 1 to 20 characterised in that selected first, second, third and fourth vias (20, 22, 69, 87) are vertically aligned and are electrically and mechanically connected.
Claim 22
Dependent Claim
11 words
The multichip module substrate made from the process of claim 1.
Claim 23
Dependent Claim
164 words
A multichip module (MCM) substrate comprising a planar ground plane, a planar voltage plane spaced from said ground plane, a planarized cover layer on said voltage plane, a plurality of planarized dielectric layers laminated between said ground plane and said voltage layer, said dielectric layers comprising a filled fluoropolymeric composite material, at least one "x" circuit line (84) on at least one of said dielectric layers, at least one "y" circuit line (67) on at least one of said dielectric layers, at least one first via (69) connecting said "x" and "y" circuit line (84, 67), at least one second via (20) extending from said ground plane through said dielectric layers, voltage plane and cover layer, said second via being electrically isolated from said voltage plane and being exposed on an outer surface of said cover layer, and at least one third via (22) extending from said voltage plane through said cover layer and being exposed on said outer surface of said cover layer.
Claim 24
Dependent Claim
20 words
The MCM substrate of claim 23 including a platform comprised of ceramic or copper, said platform supporting said MCM substrate.
References Cited (Backward Citations)
No citation records indexed.
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