Patent EP0559213A2 successfully refreshed from Google Patents.
EP0559213A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Nonvolatile semiconductor memory device
Assignee: Toshiba Corp
•
Filing: 1993-03-05
•
Granted: —
•
Expires: 2013-03-05
Abstract
Abstract In response to a plurality of address signals input from the outside in sequence, an erase information inputting section (200) controls an rease information holding section (201) corresponding to the batch erase block (203) to be erased so as to hold an erase information data. By repeating this operation in sequence, the erase information data are stored in the erase information holding sections (201) corresponding to the plural batch erase blocks (203) to be erased. Successively, on the basis of the erase information data stored in the erase information holding sections (201), block erasing sections (202) are activated to erase all the nonvolatile memory cells of each of the corresponding blocks where the erase information data are held. As a result, the erasure operation is achieved for all the batch erase blocks (203) corresponding to the erase information holding sections (201) in each of which the erase information data is held, so that a plurality of batch erase blocks (203) can be erased simultaneously, thus reducing the erasure time, as compared with the prior art memory device.
Inventors
- 👤 Hiroto Nakai
- 👤 Hideo Kato
- 👤 Kaoru Tokushige
- 👤 Masamichi Asano
- 👤 Kazuhisa Kanazawa
- 👤 Toshio Yamamura
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-08 17:20
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/10; G11C16/14; G11C16/16
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
122 words
A nonvolatile semiconductor memory device, comprising: a plurality of batch erase blocks each composed of a plurality of nonvolatile memory cells erasable simultaneously; a plurality of erase information holding means provided for each of the batch erase blocks, for holding erase information of each of said batch erase blocks; erase information inputting means for allowing the erase information to be held by said erase information holding means in sequence; and a plurality of erasing means provided for each of said batch erase blocks, for applying an erase voltage to a control electrode of each of all the nonvolatile memory cells of the corresponding batch erase block, when the erase information is held by said corresponding erase information holding means in erasure operation.
Claim 2
Dependent Claim
36 words
The nonvolatile semiconductor memory device according to claim 1, wherein a plurality of the nonvolatile memory cells can be erased simultaneously by applying the erase voltage to the control electrode of each of the memory cells.
Claim 3
Dependent Claim
48 words
The nonvolatile semiconductor memory device according to claim 1, wherein in response to a plurality of address signals input from the outside in sequence, said erase information inputting means allows the erase information to be held by said erase information holding means corresponding to the input address signals.
Claim 4
Dependent Claim
58 words
The nonvolatile semiconductor memory device according to claim 1, which further comprises block selecting means for selecting one of a plurality of said batch erase blocks, and wherein said erase information inputting means allows the erase information to be held by said erase information holding means corresponding to said batch erase block selected by said block selecting means.
Claim 5
Dependent Claim
50 words
The nonvolatile semiconductor memory device according to claim 4, which further comprises erase information holding signal outputting means for outputting an erase information holding signal, when the erase information is already held by said erase information holding means and further said block selecting means selects the corresponding batch erase block.
Claim 6
Dependent Claim
35 words
The nonvolatile semiconductor memory device according to claim 3, wherein said erase information inputting means supplies a logical product signal of a predecoder output signal and a clock signal to said erase information holding means.
Claim 7
Dependent Claim
34 words
The nonvolatile semiconductor memory device according to claim 1, wherein said erase information holding means is a latch circuit for holding a signal corresponding to a signal received by said erase information inputting means.
Claim 8
Dependent Claim
40 words
The nonvolatile semiconductor device according to claim 5, wherein said erase information holding means comprises first switching means turned on by a block selection to pass data therethrough, and holding means for holding the data passed through said switching means.
Claim 9
Dependent Claim
39 words
The nonvolatile semiconductor memory device according to claim 8, which further comprises erase information holding signal outputting means for outputting a content of said holding means and further a verify read signal when the outputted content corresponds block erasure.
Claim 10
Dependent Claim
38 words
The nonvolatile semiconductor memory device according to claim 9, wherein a memory device is determined as being defective when the number of defective erasure memory cells exceeds a predetermined value as a result of a verify read test.
Claim 11
Dependent Claim
32 words
The nonvolatile semiconductor memory device according to claim 9, which further comprises a second switching means provided in a verify read path so as to be released open only in data read.
Claim 12
Dependent Claim
26 words
The nonvolatile semiconductor memory device according to claim 8, wherein a holding signal is applied to said holding means after a holding data has been inverted.
Claim 13
Dependent Claim
189 words
A nonvolatile semiconductor memory device, comprising: a plurality of batch erase blocks each composed of a plurality of nonvolatile memory cells erasable simultaneously; block selecting means for selecting one of a plurality of said batch erase blocks and for outputting a block select signal to a node corresponding to each of the batch erase blocks ; a plurality of erase information holding means provided for each of the batch erase blocks, for holding erase information of each of the batch erase blocks and for transmitting the block select signal to the corresponding batch erase block in read operation; erase information inputting means for allowing the erase information to be held by said erase information holding means corresponding to said batch erase block selected by said block selecting means; and a plurality of memory cell selecting means provided for each of said batch erase blocks, for selecting the nonvolatile memory cells in the corresponding batch erase block in read operation, and for erasing all the nonvolatile memory cells of the corresponding batch erase blocks when the erase information is held by said corresponding erase information holding means in erasure operation.
Claim 14
Dependent Claim
159 words
A nonvolatile semiconductor memory device, comprising: a plurality of batch erase blocks each composed of a plurality of nonvolatile memory cells erasable simultaneously; a plurality of erase information holding means provided for each of the batch erase blocks, for holding erase information of each of the batch erase blocks; erase information inputting means for inputting an address signal and a block number signal on the basis of a control signal input from the outside and for allowing the erase information to be held by said erase information holding means corresponding to the batch erase blocks designated by the address signal and a plurality of the adjoining batch erase blocks designated by the block number signal; and a plurality of block erasing means provided for each of said batch erase blocks, for erasing all the nonvolatile memory cells of the corresponding batch erase blocks, when the erase information is held by said corresponding erase information holding means in erasure operation.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.