Single transistor flash electrically programmable memory

Assignee: Sony Corp

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Filing: 1993-02-24

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Granted: —

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Expires: 2013-02-24

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Abstract

Abstract The nonvolatile semiconductor memory uses a single floating gate transistor, wherein a control gate electrode (8) is negatively biased while a source region (2) is positively biased, and a writing operation is performed bit by bit by transferring electrons from the floating gate (5) into the source region through Fowler-Nordheim tunneling. And an erasing operation is performed by injecting channel hot electrons from the drain region (3) into the floating gate, or by injecting electrons from a substrate into the floating gate through Fowler-Nordheim tunneling. The source region is connected to an individual bit line, and the drain region to a common line so that over-erasing is averted.

Inventors

👤 Hideki Arakawa

Bibliographic Details

Application Number —

Jurisdiction EP

Data Source google_patents

Last Synchronized 2026-11-07 17:50

CPC Classifications

H; H10; H10B; H10B41/00; H10B41/30; H10D; H10D30/00; H10D30/60; H10D30/68; H10D30/681; H10D30/684; H10D30/685; G; G11; G11C; G11C16/00; G11C16/02; G11C16/04; G11C16/0408; G11C16/0416; G11C16/06; G11C16/08; G11C16/26; H10B69/00; H10D30/683; G11C2207/00; G11C2207/10; G11C2207/105; G11C2216/00; G11C2216/12; G11C2216/28

Claims Analysis

Total Claims: 3

Claim 1

Independent Claim 127 words

An array of flash EEPROM memory cells formed on a substrate (1) to define columns and rows, where the substrate includes a common line (COM) extending along at least one of the rows, a plurality of bit lines (BL1, BL2...) extending along respective columns, where each memory cell includes an n-type source region (2,5), a control gate (8), a floating gate (5), a channel region and an n-type drain region (3;D), and where each memory cell is programmable predominantly by tunneling electrons from its floating gate to its source region and is erasable predominantly by transferring hot electrons into its floating gate, the substrate further comprising: said drain region coupled to the common line; and said source region coupled to an individual one of the bit lines.

Claim 2

Dependent Claim 40 words

An array of flash EEPROM cells where each memory cell is programmable by injecting electrons into a floating gate (5) thereof, wherein a potential of a word line (WL1, WL2, ...) of said array is negatively biased in reading operation.

Claim 3

Dependent Claim 132 words

An address decoder circuit for a flash EEPROM comprising: an address decoding circuit having a first power supply terminal (VPP) and a second power supply terminal (VBB), wherein a potential applied to said first power supply terminal is greater than a potential applied to said second power supply terminal in reading or writing operation, and a potential applied to said second power supply terminal is greater than a potential applied to said first power supply terminal is erasing operation; a level conversion circuit (13) comprising a pair of inverters (Q5-Q6, Q7-Q8) whose input and output terminals are cross coupled to each other; and a transfer gate (12) having a terminal coupled to an output of said address decoding circuit, and another terminal coupled to an input/output terminal of said level conversion circuit.

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