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EP0553532A2
Expired / Lapsed
EP
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External memory system having programmable graphics processor for use in a video game system or the like
Assignee: A/N Inc
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Filing: 1992-08-05
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Granted: —
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Expires: 2012-08-05
Abstract
Abstract A fully programmable, graphics microprocessor is disclosed which is designed to be embodied in a removable external memory unit for connection with a host information processing system. In an exemplary embodiment, a video game system is described including a host video game system and a pluggable video game cartridge housing the graphics microprocessor. The game cartridge also includes a read-only program memory (ROM) and a random-access memory (RAM). The graphics coprocessor operates in conjunction with a three bus architecture embodied on the game cartridge. The graphics processor using this bus architecture may execute programs from either the program ROM, external RAM or its own internal cache RAM. The fully user programmable graphics coprocessor has an instruction set which is designed to efficiently implement arithmetic operations associated with 3-D graphics and, for example, includes special instructions executed by dedicated hardware for plotting individual pixels in the host video game system's character mapped display which, from the programmer's point of view, creates a "virtual" bit map by permitting the addressing of individual pixels -- even though the host system is character based. The graphics coprocessor interacts with the host coprocessor such that the graphics coprocessor's 16 general registers are accessible to the host processor at all times.
Inventors
- 👤 Jeremy E. San
- 👤 Carl N. Graham
- 👤 Ben Cheese
- 👤 Peter R. Warnes
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 21:05
CPC Classifications
G; G06; G06T; G06T1/00; G06T17/00; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3802; G06F9/3814; G06F9/3877; G06F9/3879; G06T1/20; A; A63; A63F; A63F2300/00; A63F2300/20; A63F2300/203
Claims Analysis
Total Claims: 39
Claim 1
Independent Claim
126 words
In an information processing system (19, 20) having a host processing unit (20) for executing a videographics program stored at least in part in an external memory (20) in an external memory system (19), said external memory system characterized by: at least one connector (1) for coupling said external memory system to said host processing system; an external memory (10) for storing a first set of program instructions of said videographics program for execution by said host processing unit and for storing a second set of instructions of said videographics program; and a graphics processor (2) coupled to said external memory (10) and coupled, in use, to said host processing unit (20) via said at least one connector (1), for executing said second set of instructions.
Claim 2
Dependent Claim
35 words
An external memory system according to claim 1, wherein said host processing unit (20) is a video game system main processing unit and said external memory system is embodied within a video game cartridge (19).
Claim 3
Dependent Claim
88 words
An external memory system according to claim 1, further including an external memory bus coupled to said external memory (10) and said graphics processor (2) for transmitting address, data and control information; a random access memory unit (6, 8), a random access memory unit bus, coupled to said random access memory unit (6, 8) and said graphics processor (2), for transmitting address, data and control information; and a host processing unit bus for transmitting address, data and control information between said graphics processor and said host processing unit.
Claim 4
Dependent Claim
34 words
An external memory system according to claim 3, wherein said graphics processor includes means for controlling access to at least one of said external memory bus and said random access memory unit bus (131).
Claim 5
Dependent Claim
42 words
An external memory system according to claim 1, wherein said graphics processor (2) includes means for receiving address information (HA, 133) from said host processing unit for identifying the external memory location storing an instruction to be executed by the graphics processor.
Claim 6
Dependent Claim
53 words
An external memory system according to claim 1, wherein said graphics processor includes an arithmetic and logic unit (50) for executing at least some of said second set of instructions stored in said external memory and a plotting circuit (52) for executing at least one display related instruction stored in said external memory.
Claim 7
Dependent Claim
46 words
An external memory system according to claim 6, further including a first data source bus (X), a second data source bus (Y) and a data destination bus (Z), each of said buses being coupled to said arithmetic and logic unit (50) and said plotting circuit (52).
Claim 8
Dependent Claim
44 words
An external memory system according to claim 1, said graphics processor further including a cache controller (68) and a cache memory (94) coupled to said cache controller (68), said graphics processor including means for executing instructions stored in said cache memory (95, 60, 50).
Claim 9
Dependent Claim
47 words
An external memory system according to claim 1, wherein said graphics processor includes a plurality of registers (76), said graphics processor further including means responsive to the accessing of a predetermined one of said plurality of registers (R14) for automatically initiating an external memory fetching operation (104).
Claim 10
Dependent Claim
31 words
An external memory system according to claim 1, wherein said external memory is a program read-only memory (ROM) and further including a random access memory (RAM) coupled to said graphics processor.
Claim 11
Dependent Claim
24 words
An external memory system according to claim 1, wherein said graphics processor and said host processing unit are operable to execute instructions in parallel.
Claim 12
Dependent Claim
21 words
An external memory system according to claim 1, wherein said graphics processor includes means for pipelining instructions being executed (62, 60).
Claim 13
Dependent Claim
38 words
An external memory system according to claim 1, wherein said graphics processor includes means for decoding (60) said second set of instructions, and look-ahead means (551) for processing operation codes in advance of the associated instruction being decoded.
Claim 14
Dependent Claim
48 words
An external memory system according to claim 1, wherein said information processing system (20) includes a display (36) for displaying an object and wherein said second set of instructions includes instructions for rotating said object, said graphics processor includes means for executing said instructions for rotating said object.
Claim 15
Dependent Claim
93 words
A video game system (19, 20) for use with a television type display (36) characterized by: a game microprocessor (22) for executing instructions of a video game program, and a picture processing unit (24) coupled to said game microprocessor for performing picture processing tasks under the control of said game microprocessor (22); a program memory (10) for storing said video game program; and a programmable graphics processor (2) coupled to said program memory and connected in use to said game microprocessor (22) for executing at least some of said video game program instructions.
Claim 16
Dependent Claim
89 words
A video game system according to claim 15, further including a program memory bus coupled to said program memory (10) and said programmable graphics processor (2) for transmitting address, data and control information; a random access memory unit, a random access memory unit bus, coupled to said random access memory unit (6, 8) and said programmable graphics processor (2) for transmitting address, data and control information; and a game microprocessor bus for transmitting address, data and control information between said programmable graphics processor (2) and said game microprocessor (22).
Claim 17
Dependent Claim
55 words
A video game system according to claim 15, wherein said programmable graphics processor (2) includes an arithmetic and logic unit (50) for executing at least some of said second portion of instructions stored in said program memory and a plotting circuit (52) for executing at least one display related instruction stored in said program memory.
Claim 18
Dependent Claim
63 words
A video game system according to claim 15, wherein said programmable graphics processor (2) further includes a cache controller (68) and a cache memory (94) coupled to said cache controller (68), said programmable graphics processor including means for executing instructions stored in said cache memory (95, 60, 50), whereby said graphics processor and said game microprocessor are able to execute instructions in parallel.
Claim 19
Dependent Claim
46 words
A video game system according to claim 15, wherein said game microprocessor (22) and picture processing unit (24) are embodied in a video game system main processing unit (20) and said program memory (10) and graphics processor (2) are embodied within a video game cartridge (19).
Claim 20
Dependent Claim
71 words
For use in an information processing system (19, 20) having a first processing unit (20) for executing at least a first portion of a videographics program stored in an external memory (10), a programmable graphics processor characterized by: means for receiving instructions from a second portion of said videographics program from said external memory (10); and means for executing at least said second portion of said videographics programs (60, 50, 52).
Claim 21
Dependent Claim
36 words
A programmable graphics processor according to claim 20, further including means for receiving address information from said first processing unit for identifying the external memory location storing an instruction to be executed by the graphics processor.
Claim 22
Dependent Claim
42 words
A programmable graphics processor according to claim 21, wherein said means for receiving address information includes a external memory bank register for receiving address information identifying an external memory bank and a program counter for identifying a location within said memory bank.
Claim 23
Dependent Claim
53 words
A programmable graphics processor according to claim 20, wherein said graphics processor includes status register means for storing a plurality of graphics processor status indications including an indication that the graphics processor is currently in operation, and an indication that the graphics processor has sent an interrupt signal to the first processing unit.
Claim 24
Dependent Claim
55 words
An external memory system according to claim 20, wherein said graphics processor includes an arithmetic and logic unit (50) for executing at least some of said second portion of said videographics program stored in said external memory and a plotting circuit (52) for executing at least one display related instruction stored in said external memory.
Claim 25
Dependent Claim
44 words
A programmable graphics processor according to claim 24, further including a first data source bus (X), a second data source bus (Y) and a data destination bus (Z), each of said buses being coupled to said arithmetic and logic unit and said plotting circuit.
Claim 26
Dependent Claim
37 words
A programmable graphics processor according to claim 20, further including a cache controller (68) and a cache memory (94) coupled to said cache controller, and means for executing instructions stored in said cache memory (95, 60, 50).
Claim 27
Dependent Claim
91 words
A programmable graphics processor according to claim 20, further including: means for executing at least one instruction (50); a status register for storing a plurality of status conditions; an instruction decoder (62) responsive to the state of at least one of said status conditions for causing said at least one predetermined instruction to control said means for executing to initiate a first operation if said status register is one state and for causing said means for executing to initiate a second operation if said status register is in a second state.
Claim 28
Dependent Claim
33 words
A programmable graphics processor according to claims 20 wherein said information processing system associated with display and wherein said graphics processor coacts with said first processing unit to control rotation of displayed objects.
Claim 29
Dependent Claim
26 words
A programmable graphics processor according to claim 28, wherein said means for executing includes plotting circuitry (52) for converting pixel-based format data into character-based format data.
Claim 30
Dependent Claim
75 words
A graphics processor (2) for use with a host processing system (20) and a program memory (10) for storing a videographics program, said graphics processor characterized by: an arithmetic and logic unit (50) for executing instructions stored in said program memory; a program memory controller (104) for controlling access to said program memory and for selectively enabling at least one of said host processing system (10) and said graphics processor to access said program memory.
Claim 31
Dependent Claim
28 words
A graphics processor according to claim 30, further including a cache memory (94), said program memory controller (104) including means for loading said cache memory with program instructions.
Claim 32
Dependent Claim
41 words
A graphics processor according to claim 30, wherein said graphics processor (2) is coupled to a program memory address bus and said program memory controller includes a multiplexer (414) for selecting an address to place on said program memory address bus.
Claim 33
Dependent Claim
41 words
A graphics processor according to claim 33, further including a plurality of registers (76), wherein said program memory controller (106) includes means for automatically initiating a program memory data fetch in response to one of said plurality of registers being accessed.
Claim 34
Dependent Claim
35 words
A graphics processor according to claim 30, wherein said graphics processor (2) is coupled to a random access memory (RAM) (6, 8) and further includes a RAM controller (88) for controlling access to said RAM.
Claim 35
Dependent Claim
82 words
A graphics processor (2) for use with a host processing system (20), a program memory (10) for storing a videographics program, and a random access memory (RAM) (6, 8) said graphics processor characterized by: means for receiving a RAM addresses from said host processing system (HA); graphics processing means for generating RAM addresses; and a RAM controller (88) for selecting between a host processing system RAM address and a graphics processing means generated RAM address and for coupling same to said RAM.
Claim 36
Dependent Claim
64 words
A graphics processor according to claim 35, further including at least one status register wherein said RAM controller includes multiplexer means (308) for receiving a host processing system generated address (HA) and a graphics processing means generated address (DEOTADOR), and for coupling one of said addresses to said RAM depending upon the state of at least one status bit stored in said status register.
Claim 37
Dependent Claim
84 words
In an information processing system (19, 20) having a host processing system (20), an external memory system (19) coupled to said host system, said external memory system characterized by: a program memory (10); an additional memory (6, 8); and a graphics processor (2) coupled to said program memory (10) and said additional memory (6, 8): said graphics processor including: a program memory controller (104) for controlling access to said program memory; and an additional memory controller (88) for controlling access to said additional memory.
Claim 38
Dependent Claim
30 words
An eternal memory system according to claim 57, wherein said additional controller (88) includes means for determining priority between a plurality of received requests for access to said additional memory.
Claim 39
Dependent Claim
38 words
An external memory system according to claim 38, further including plotting circuitry (52), and wherein said additional memory controller (88) receives a plot request signal indicating that a memory access is required for a plotting operation being performed.
References Cited (Backward Citations)
No citation records indexed.
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