Patent US3978581A successfully refreshed from Google Patents.
Patent EP0552968A2 successfully refreshed from Google Patents.
EP0552968A2
Expired / Lapsed
EP
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Semiconductor device including a wiring layer
Assignee: Samsung Electronics Co Ltd
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Filing: 1993-01-22
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Granted: —
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Expires: 2013-01-22
Abstract
Abstract A semiconductor device comprising a wiring layer having a novel contact structure. The semiconductor device includes a semiconductor substrate (31, 51), an insulating layer having an opening (contact hole via a recess), a reactive spacer (37a) formed on the sidewall of the opening or a reactive layer (57a) formed on the sidewall and on the bottom surface of the opening and a conductive layer (39a, 59a) formed on the insulating layer which completely fills the opening. Since the reactive spacer or layer (37a, 57a) is formed on the sidewall of the opening, when the conductive layer material is deposited, large islands will form to become large grains of the sputtered Al film. Also, providing the reactive spacer or layer (37a, 57a) improves the reflow of the conductive layer (39, 59) during a heat-treating step for filling the opening at a high temperature below a melting temperature. This, complete filling of the opening with sputtered Al can be ensured. All the contact holes, being less than 1 µm in size and having an aspect ratio greater than 1.0, can be completely filled with Al, to thereby enhance the reliability of the wiring of a semiconductor device.
Inventors
- 👤 Sang-In Lee
- 👤 Chang-Soo Park
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-01 18:26
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/032; H10W20/054; H10W20/033; H10W20/035; H10P; H10P14/00; H10P14/40; H10P14/418; H10P95/00; H10W20/034; H10W20/047; H10W20/049; H10W20/056; H10W20/059; H10W20/063; H10W20/0633; H10W20/071; H10W20/081; H10W20/40; H10W20/41; H10W20/42; H10W20/425
Claims Analysis
Total Claims: 46
Claim 1
Independent Claim
79 words
A semiconductor device including a wiring layer comprising: a semiconductor substrate (31, 101); an insulating layer (34, 108) having an opening therein on said semiconductor substrate, said opening exposing a portion of a surface of an underlying layer of said insulating layer; a reactive spacer (37a, 111a) formed on a sidewall of said opening; and a conductive layer (39a, 112) formed on said insulating layer, on said reactive spacer and on said exposed surface portion of said underlying layer.
Claim 2
Dependent Claim
76 words
A semiconductor device including a wiring layer comprising: a semiconductor substrate (31); an insulating layer (34) having an opening therein on said semiconductor substrate, said opening exposing a portion of a surface of an underlying layer of said insulating layer; a reactive spacer (37a) formed on a sidewall of said opening; a conductive layer (39a) formed on said insulating layer and completely filling said opening; and a further conductive layer (41a,61a) formed on said conductive layer.
Claim 3
Dependent Claim
75 words
A semiconductor device including a wiring layer comprising: a semiconductor substrate (51); an insulating layer (54) having an opening therein on said semiconductor substrate, said opening exposing a portion of a surface of an underlying layer of said insulating layer; a reactive layer (57a) formed on a sidewall of said opening and on said exposed portion of said underlying layer; and a conductive layer (59a) formed on said insulating layer and completely filling said opening.
Claim 4
Dependent Claim
29 words
A semiconductor device as claimed in claim 1 or 3 further comprising a further conductive layer (61a) formed on said conductive layer having a planarized surface over said opening.
Claim 5
Dependent Claim
23 words
A semiconductor device as claimed in claims 2 or 4, wherein said further conductive layer (61a;41a) has a planarized surface over said opening.
Claim 6
Dependent Claim
26 words
A semiconductor device as claimed in any of claims 2, 4 or 5, wherein said further conductive layer (61a) comprises a metal having no Si component.
Claim 7
Dependent Claim
32 words
A semiconductor device as claimed in any preceding claim, wherein said opening extends to the surface of said semiconductor substrate, thereby exposing a portion of the surface of said semiconductor substrate (31).
Claim 8
Dependent Claim
33 words
A semiconductor device as claimed in any of claims 1 to 6, wherein said opening is a via which exposes a portion of a lower wiring layer (106) underlying said insulating layer (108).
Claim 9
Dependent Claim
33 words
A semiconductor device as claimed in any preceding claim, wherein said reactive spacer (37a, 111a) or layer (57a) comprises an element which lowers the melting point of a material of said conductive layer.
Claim 10
Dependent Claim
27 words
A semiconductor device as claimed in claim 9, wherein said element is any one selected from a group consisting of Ge, Mg, Sn, In, Pb and Zn.
Claim 11
Dependent Claim
36 words
A semiconductor device as claimed in any of claims 1 to 8, wherein said reactive spacer (37a, 111a) or layer (57a) comprises any one selected from a group consisting of transition metals and transition metal compounds.
Claim 12
Dependent Claim
34 words
A semiconductor device as claimed in claim 11, wherein said reactive spacer (37a, 111a) or layer (57a) comprises any one selected from a group consisting of Ti, Mo, Ta and W and compounds thereof.
Claim 13
Dependent Claim
32 words
A semiconductor device as claimed in any preceding claim, wherein said conductive layer (39a) comprises a first metal layer having a Si component and a second metal layer having no Si component.
Claim 14
Dependent Claim
32 words
A semiconductor device as claimed in any of claims 1 to 12, wherein said conductive layer (39a) comprises a metal having not more than 0.5 percent by weight of a Si component.
Claim 15
Dependent Claim
48 words
A semiconductor device as claimed in any preceding claim, further comprising a diffusion barrier layer (35) formed on the surface of said insulating layer, on a sidewall of said opening and on an exposed surface of said underlying layer, and under said conductive layer (39a, 41a, 61a, 112).
Claim 16
Dependent Claim
31 words
A semiconductor device as claimed in claim 15, wherein said diffusion barrier layer (35) comprises at least one material selected from a group consisting of transition metals and transition metal compounds.
Claim 17
Dependent Claim
39 words
A semiconductor device as claimed in claim 15 or 16, wherein said diffusion barrier layer (35) comprises a first diffusion barrier layer composed of a transition metal, and a second diffusion barrier layer composed of a transition metal compound.
Claim 18
Independent Claim
82 words
A method for manufacturing a semiconductor device including a wiring layer comprising the steps of: forming an insulating layer (34) on a semiconductor substrate (31); providing said insulating layer (34) with an opening exposing a portion of a surface of an underlying layer of said insulating layer (34); forming a reactive spacer (37a) on a sideswall of said opening;and forming a conductive layer (39) on said insulating layer, on said reactive spacer, and on said exposed surface portion of said underlying layer.
Claim 19
Dependent Claim
32 words
A method for manufacturing a semiconductor device as claimed in claim 18, wherein said reactive spacer (37a) comprises an element which lowers the melting point of a material of said conductive layer.
Claim 20
Dependent Claim
31 words
A method for manufacturing a semiconductor device as claimed in claim 19, wherein said element is any one selected from a group consisting of Ge, Mg, Sn, In, Pb and Zn.
Claim 21
Dependent Claim
33 words
A method for manufacturing a semiconductor device as claimed in claim 18, wherein said reactive spacer (37a) comprises any one material selected from a group consisting of transition metals and transition metal compounds.
Claim 22
Dependent Claim
35 words
A method for manufacturing a semiconductor device as claimed in claim 21, wherein said reactive spacer (37a) comprises any one material selected from a group consisting of Ti, Mo, Ta and W and compounds thereof.
Claim 23
Independent Claim
78 words
A method for manufacturing a semiconductor device as claimed in any of claims 18 to 22, wherein said reactive spacer (37a) is formed by depositing a reactive material to form a reactive material layer (37) on said insulating layer (34), on a sidewall of said opening and on said exposed surface portion of said underlying layer, and selectively removing said reactive material layer (37) on said insulating layer (34) and said exposed surface portion of said underlying layer.
Claim 24
Dependent Claim
25 words
A method for manufacturing a semiconductor device as claimed in claim 23, wherein said reactive material layer (37) is selectively removed by an etch-back process.
Claim 25
Independent Claim
52 words
A method for manufacturing a semiconductor device as claimed in any of claims 18 to 24 further comprising the step of heat-treating said conductive layer (39) for an appropriate time to fill up said opening with the material of said conductive layer (39), without breaking vacuum after forming said conductive layer (39).
Claim 26
Independent Claim
69 words
A method for manufacturing a semniconductor device as claimed in any of claims 18 to 25, wherein said opening extends to a surface of said semiconductor substrate (31), thereby exposing a portion of the surface of said semiconductor substrate (31); and said conductive layer (39) is formed on said insulating layer (34), on the inner surface of said opening and on said exposed surface of said semiconductor substrate (31).
Claim 27
Independent Claim
53 words
A method for manufacturing a semiconductor device as claimed in any of claims 18 to 26, wherein said conductive layer (39) is obtained by sequentially depositing a first metal having a Si component to form a first metal layer and a second metal having no Si component to form a second metal layer.
Claim 28
Dependent Claim
45 words
A method for manufacturing a semiconductor device as claimed in claim 27, wherein said conductive layer (39) heat-treating step is carried out at a temperature ranging from 0.8Tm to Tm, where Tm is the melting temperature of said first metal, for at least one minute.
Claim 29
Dependent Claim
31 words
A method for manufacturing a semiconductor device as claimed in claim 27 or 28, wherein said first metal and said second metal are deposited in a vacuum at a low temperature.
Claim 30
Dependent Claim
21 words
A method for manufacturing a semiconductor device as claimed in claim 29, wherein said low temmperature is a temmperature below 150°C.
Claim 31
Independent Claim
41 words
A method for manufacturing a semiconductor device as claimed in any of claims 18 to 26, wherein said conductive layer (39) is formed by depositing a metal a having not more than about 0.5 percent by weight of a Si component.
Claim 32
Dependent Claim
35 words
A method for manufacturing a semiconductor device as claimed in claim 25, further comprising the step of forming a further conductive layer (41) on said conductive layer (39) by depositing a metal after-said heat-treating step.
Claim 33
Dependent Claim
28 words
A method for mnanufacturing a semniconductor device as claimed in claim 32, wherein said further conductive layer (41) is formed by depositing a metal having no Si component.
Claim 34
Dependent Claim
27 words
A method for manufacturing a semiconductor device as claimed in claim 33, wherein said metal of said further conductive layer is deposited at a temperature below 350°C.
Claim 35
Independent Claim
39 words
A method for manufacturing a semiconductor device as claimed in any of claims 32 to 34, further comprising the step of heat-treating said further conductive layer (41) thereby to planarize the resultant surface of said further conductive layer (41).
Claim 36
Dependent Claim
47 words
A method for manufacturing a semiconductor device as claimed in claim 35, wherein said heat-treating step of said further conductive layer (41) is carried out at a temperature ranging from 0.8Tm to Tm, where Tm is the melting temperature of said metal, for at least one minute.
Claim 37
Independent Claim
55 words
A method for manufacturing a semiconductor device as claimed in any of claims 18 to 36, further comprising the step of forming a diffusion barrier layer (35) on the surface of said insulating layer, on the inner surface of said opening, and on an exposed surface of said underlying layer before forming said conductive layer.
Claim 38
Dependent Claim
87 words
A method for manufacturing a semiconductor device as claimed in claim 37, wherein said diffusion barrier layer (35) forming step comprises the steps of: forming a first diffusion barrier layer on the surfaces of said insulating layer, on the inner surface of said opening, and on an exposed surface of said underlying layer; forming a second diffusion barrier layer on said first diffusion barrier layer; and heat-treating said diffusion barrier layer at a temmperature of about 450-600°C in a nitrogen or ammonia atmosphere for approximately 30-60 minutes.
Claim 39
Independent Claim
86 words
A method for manufacturing a semiconductor device including a wiring layer comprising the steps of: forming an insulating layer (54) on a semiconductor substrate (51); providing said insulating layer (54) with an opening exposing a portion of a surface of an underlying layer of said insulating layer (54); forming a reactive layer (57a) on a sidewall of said opening and on said exposed surface portion of said underlying layer; and forming a conductive layer (59) on said insulating layer (54) and on said reactive layer (57a).
Claim 40
Dependent Claim
48 words
A method for manufacturing a semiconductor device as claimed in claim 39 further comprising the step of heat-treating said conductive layer (59) for an appropriate time to fill up said opening with the material of said conductive layer (59) without breaking vacuum after forming said conductive layer (59).
Claim 41
Dependent Claim
64 words
A semiconductor device including a wiring layer comprising: a semiconductor substrate (91); an insulating layer (94) having a recessed portion therein on said semiconductor substrate; a reactive spacer (96) formed on a sidewall of said recessed portion; and a conductive layer (99a) on said recessed portion and on said reactive spacer, said conductive layer completely filling said recessed portion and having a planarized surface.
Claim 42
Dependent Claim
59 words
A semiconductor device including a wiring layer comprising: a semiconductor substrate (71); an insulating layer (74) having a recessed portion therein on said semiconductor substrate; a reactive layer (76) formed on an inner surface of said recessed portion;and a conductive layer (79a) on said reactive layer, said conductive layer completely filling said recessed portion and having a planarized surface.
Claim 43
Independent Claim
104 words
A method for manufacturing a semiconductor device including a wiring layer comprising the steps of: forming an insulating layer (94) having a recessed portion therein on a semiconductor substrate; forming a reactive spacer (96) on a sidewall of said recessed portion; forming a conductive layer (99) on said insulating layer and on said reactive spacer, and heat-treating said conductive layer (99) for an appropriate time at a high temperature below the melting point of a material of said first conductive layer to completely fill up said recessed portion with the material of said conductive layer, without breaking vacuum after forming said conductive layer (99).
Claim 44
Independent Claim
108 words
A method for manufacturing a semiconductor device including a wiring layer comprising the steps of: forming an insulating layer (74) having a recessed portion therein on a semiconductor substrate (71); forming a reactive layer (76) on an inner surface of said recessed portion; forming a conductive layer (79) on said insulating layer and on said reactive layer; and heat-treating said first conductive layer (79) for an appropriate time at a high temmperature below the melting point of a material of said first conductive layer to completely fill up said recessed portion with the material of said first conductive layer, without breaking vacuum after forming said conductive layer (79).
Claim 45
Dependent Claim
63 words
A semiconductor device comprising a reactive spacer (37a, 96 and 111a) formed on the sidewall of a recessed portion, which improves step coverage of a conductive layer in a depositing step and enhances reflow of a material of said conductive layer in a step of reflowing of said material of said conductive layer by heat-treating said conductive layer, after forming said conductive layer.
Claim 46
Dependent Claim
63 words
A semiconductor device comprising a reactive layer (57a, 76 and 116) formed on the inner surface a recessed portion, which improves step coverage of a conductive layer in a depositing step and enhances reflow of a material of said conductive layer in a step of reflowing of said material of said conductive layer by heat-treating said conductive layer, after forming said conductive layer.
References Cited (Backward Citations)
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