Patent US3900544A successfully refreshed from Google Patents.
Patent EP0551110A2 successfully refreshed from Google Patents.
EP0551110A2
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EP
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Compound semiconductor devices
Assignee: Mitsubishi Electric Corp
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Filing: 1993-01-07
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Granted: —
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Expires: 2013-01-07
Abstract
Abstract A field effect transistor includes a III-V compound semiconductor substrate (1) having a surface, III-V compound semiconductor layers successively disposed on said surface, including, from below, an InAlAs layer (5), an InP layer (6), and an InGaAs layer (7), a gate recess penetrating through the InGaAs layer (7) and the InP layer (6), and a gate electrode (8) in contact with the InAlAs layer (5). In this structure, the contact surface of the gate electrode (8) with the InAlAs layer (5) is on the same level with the interface between the InP layer (6) and the InAlAs layer (5). In producing the gate recess, the InGaAs layer (7) is first etched by an etchant comprising hydrogen peroxide water and at least one of tartaric acid, phosphoric acid, and sulfuric acid, using the InP layer (6) as an etching stopper layer, and then the InP layer (6) is etched by hydrochloric acid, using the InAlAs layer (5) as an etching stopper layer. Therefore, the depth of the gate recess is accurately determined by the etching stopper layers, resulting in field effect transistors with uniform electric characteristics.
Inventors
- 👤 Masahiko c/o Mitsubishi Denki K.K. Nakanishi
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-29 18:57
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D10/00; H10D10/01; H10D10/021; H10D10/80; H10D10/821; H10D30/015; H10D30/051; H10D30/061; H10D30/0612; H10D30/40; H10D30/47; H10D30/471; H10D30/473; H10D30/4732; H10D30/80; H10D30/87; H10D30/877; H10D62/00; H10D62/80; H10D62/82; H10D62/824; H10D84/00; H10D84/01; H10D84/02; H10D84/05; H10P; H10P50/00; H10D62/85; H10D62/854; H10D84/0112; H10D84/0123
Claims Analysis
Total Claims: 31
Claim 1
Independent Claim
102 words
A field effect transistor including a plurality of III-V compound semiconductor layers successively disposed on a surface of a III-V compound semiconductor substrate, characterized by: a laminated structure comprising, from below, an InAlAs layer (5), an InP layer (6), and an InGaAs layer (7); a gate recess penetrating through said InGaAs layer (7) and said InP layer (6); a gate electrode (8) being in contact with said InAlAs layer (5); and the contact surface of said gate electrode (8) with said InAlAs layer (5) being on the same level with the interface between said InP (6) layer and said InAlAs layer (5).
Claim 2
Dependent Claim
91 words
A field effect transistor of claim 1 wherein said gate recess is formed by removing a portion of said InGaAs layer (7) by a first etchant which etches a compound semiconductor including As but does not etch a compound semiconductor including P, using said InP layer (6) as an etching stopper layer, and removing a portion of said InP layer (6) by a second etchant which etches the compound semiconductor including P but does not etch the compound semiconductor including As, using said InAlAs layer (5) as an etching stopper layer.
Claim 3
Dependent Claim
33 words
The field effect transistor of claim 2 wherein said first etchant comprises hydrogen peroxide water and one selected from tartaric acid, phosphoric acid, and sulfuric acid, and said second etchant comprises hydrochloric acid.
Claim 4
Dependent Claim
98 words
A field effect transistor including a plurality of III-V compound semiconductor layers successively disposed on a surface of a III-V compound semiconductor substrate (1), characterized by: a laminated structure comprising, from below, an InAlAs layer (5), an InP layer (6), and an InGaAs layer (7); a gate recess penetrating through said InGaAs layer (7); a gate electrode (8) being in contact with said InP layer (6); and the contact surface of said gate electrode (8) with said InP layer (6) being on the same level with the interface between said InGaAs layer (7) and said InP layer (6).
Claim 5
Dependent Claim
52 words
A field effect transistor of claim 1 wherein said gate recess is formed by removing a portion of said InGaAs layer (7) by a first etchant which etches a compound semiconductor including As but does not etch a compound semiconductor including P using said InP layer (6) as an etching stopper layer.
Claim 6
Dependent Claim
107 words
A field effect transistor including a plurality of III-V compound semiconductor layers successively disposed on a surface of a III-V compound semiconductor substrate (1), characterized by: a laminated structure comprising a lower InAlAs layer (5), an InP layer (6), and an upper InAlAs layer (11); a gate recess penetrating through said upper InAlAs layer (11) and said InP layer (6); a gate electrode (8) being in contact with said lower InAlAs layer (5); and the contact surface of said gate electrode (8) with said lower InAlAs layer (5) being on the same level with the interface between said InP layer (6) and said lower InAlAs layer (5).
Claim 7
Dependent Claim
100 words
A field effect transistor including a plurality of III-V compound semiconductor layers successively disposed on a surface of a III-V compound semiconductor substrate (1), characterized by: a laminated structure comprising a lower InAlAs layer (5), an InP layer (6), and an upper InAlAs layer (11); a gate recess penetrating through said upper InAlAs layer (11); a gate electrode (8) being in contact with said InP layer (6); and the contact surface of said gate electrode (8) with said InP layer (6) being on the same level with the interface between said upper InAlAs layer (11) and said InP layer (6).
Claim 8
Dependent Claim
24 words
A semiconductor device comprising said field effect transistor of claim 1 and said field effect transistor of claim 4, produced on the same substrate.
Claim 9
Dependent Claim
24 words
A semiconductor device comprising said field effect transistor of claim 6 and said field effect transistor of claim 7, produced on the same substrate.
Claim 10
Dependent Claim
24 words
A semiconductor device comprising said field effect transistor of claim 1 and said field effect transistor of claim 6, produced on the same substrate.
Claim 11
Dependent Claim
24 words
A semiconductor device comprising said field effect transistor of claim 1 and said field effect transistor of claim 7, produced on the same substrate.
Claim 12
Dependent Claim
24 words
A semiconductor device comprising said field effect transistor of claim 4 and said field effect transistor of claim 6, produced on the same substrate.
Claim 13
Dependent Claim
24 words
A semiconductor device comprising said field effect transistor of claim 4 and said field effect transistor of claim 7, produced on the same substrate.
Claim 14
Dependent Claim
157 words
A semiconductor device including a plurality of III-V compound semiconductor layers successively disposed on a surface of a III-V compound semiconductor substrate (1), characterized by: a laminated structure comprising a lower InAlAs layer (5), a lower InP layer (6), an upper InAlAs layer (11), and an upper InP layer (12); a field effect transistor (200b) including a gate electrode (8b) being in contact with said lower InAlAs layer (5), the contact surface of said gate electrode (8b) with said lower InAlAs layer (5) being on the same level with the interface between said lower InP layer (6) and said lower InAlAs layer (5); and a field effect transistor (200a) including a gate electrode (8a) being in contact with said upper InAlAs layer (11), the contact surface of said gate electrode (8a) with said upper InAlAs layer (11) being on the same level with the interface between said upper InP layer (12) and said upper InAlAs layer (11).
Claim 15
Dependent Claim
157 words
A semiconductor device including a plurality of III-V compound semiconductor layers successively disposed on a surface of a III-V compound semiconductor substrate (1), characterized by: a laminated structure comprising a lower InAlAs layer (5), a lower InP layer (6), an upper InAlAs layer (11), and an upper InP layer (12); a field effect transistor (300b) including a gate electrode (8b) being in contact with said lower InP layer (6), the contact surface of said gate electrode (8b) with said lower InP layer (6) being on the same level with the interface between said lower InAlAs layer (11) and said lower InP layer (6); and a field effect transistor (300a) including a gate electrode (8a) being in contact with said upper InP layer (12), the contact surface of said gate electrode (8a) with said upper InP layer (12) being on the same level with the interface between said upper InAlAs layer (70) and said upper InP layer (12).
Claim 16
Dependent Claim
88 words
A heterojunction bipolar transistor including a plurality of III-V compound semiconductor layers successively disposed on a surface of a III-V compound semiconductor substrate (1), characterized by: a laminated structure comprising, from below, an InGaAs layer (101), an InP layer (102), and an InAlAs layer (103); base electrodes (106) being in contact with said InGaAs layer (101); and the contact surface of said base electrodes (106) with said InGaAs layer (101) being on the same level with the interface between said InP layer (102) and said InGaAs layer (101).
Claim 17
Dependent Claim
88 words
A heterojunction bipolar transistor including a plurality of III-V compound semiconductor layers successively disposed on a surface of a III-V compound semiconductor substrate (1), characterized by: a laminated structure comprising, from below, an InGaAs layer (101), an InP layer (102), and an InAlAs layer (103); base electrodes (106) being in contact with said InP layer (102); and the contact surface of said base electrodes (106) with said InP layer (102) being on the same level with the interface between said InAlAs layer (103) and said InP layer (102).
Claim 18
Dependent Claim
106 words
A field effect transistor including a plurality of III-V compound semiconductor layers successively disposed on a surface of a III-V compound semiconductor substrate (14), characterized by: one of laminated structures of AlGaAs(16)/InP(6)/GaAs(17) from below, AlGaAs(16)/InP(6)/InGaAs(7) from below, lower GaAs(18)/InP(6)/upper GaAs(17), and GaAs(18)/InP(6)/InGaAs(7) from below; a gate electrode (8) being in contact with said AlGaAs layer (16) or said lower GaAs layer (18); and the contact surface of said gate electrode (8) with said AlGaAs layer (16) or said lower GaAs layer (18) being on the same level with the interface between said InP layer (6) and said AlGaAs layer (16) or said lower GaAs layer (18).
Claim 19
Dependent Claim
94 words
A field effect transistor including a plurality of III-V compound semiconductor layers successively disposed on a surface of a III-V compound semiconductor substrate (14), characterized by: one of laminated structures of AlGaAs(16)/InP(6)/GaAs(17) from below, AlGaAs(16)/InP(6)/InGaAs(7) from below, lower GaAs(18)/InP(6)/upper GaAs(17), and GaAs(18)/InP(6)/InGaAs(7) from below; a gate electrode (8) being in contact with said InP layer (6); and the contact surface of said gate electrode (8) with said InP layer (6) being on the same level with the interface between said InP (6) layer and said upper GaAs layer (17) or said InGaAs layer (7).
Claim 20
Dependent Claim
107 words
A field effect transistor including a plurality of III-V compound semiconductor layers successively disposed on a surface of a III-V compound semiconductor substrate (14), characterized by: a laminated structure comprising a lower AlGaAs layer (16), an InP layer (6), and an upper AlGaAs layer (20); a gate recess penetrating through said upper AlGaAs layer (20) and said InP layer (6); a gate electrode (8) being in contact with said lower AlGaAs layer (16); and the contact surface of said gate electrode (8) with said lower AlGaAs layer (16) being on the same level with the interface between said InP layer (6) and said lower AlGaAs layer (16).
Claim 21
Dependent Claim
100 words
A field effect transistor including a plurality of III-V compound semiconductor layers successively disposed on a surface of a III-V compound semiconductor substrate (14), characterized by: a laminated structure comprising a lower AlGaAs layer (16), an InP layer (6), and an upper AlGaAs layer (20); a gate recess penetrating through said upper AlGaAs layer (20); a gate electrode (8) being in contact with said InP layer (6); and the contact surface of said gate electrode (8) with said InP layer (6) being on the same level with the interface between said upper AlGaAs layer (20) and said InP layer (6).
Claim 22
Dependent Claim
24 words
A semiconductor device comprising said field effect transistor of claim 18 and said field effect transistor of claim 19, produced on the same substrate.
Claim 23
Dependent Claim
24 words
A semiconductor device comprising said field effect transistor of claim 20 and said field effect transistor of claim 21, produced on the same substrate.
Claim 24
Dependent Claim
24 words
A semiconductor device comprising said field effect transistor of claim 18 and said field effect transistor of claim 20, produced on the same substrate.
Claim 25
Dependent Claim
24 words
A semiconductor device comprising said field effect transistor of claim 18 and said field effect transistor of claim 21, produced on the same substrate.
Claim 26
Dependent Claim
24 words
A semiconductor device comprising said field effect transistor of claim 19 and said field effect transistor of claim 20, produced on the same substrate.
Claim 27
Dependent Claim
24 words
A semiconductor device comprising said field effect transistor of claim 19 and said field effect transistor of claim 21, produced on the same substrate.
Claim 28
Dependent Claim
155 words
A semiconductor device including a plurality of III-V compound semiconductor layers successively disposed on a surface of a III-V compound semiconductor substrate (14), characterized by: a laminated structure comprising a lower AlGaAs layer (16), a lower InP layer (6), an upper AlGaAs layer (20), and an upper InP layer (12); a field effect transistor including a gate electrode (8) being in contact with said lower AlGaAs layer (16), the contact surface of said gate electrode (8) with said lower AlGaAs layer (16) being on the same level with the interface between said lower InP layer (6) and said lower AlGaAs layer (16); and a field effect transistor including a gate electrode (8) being in contact with said upper AlGaAs layer (20), the contact surface of said gate electrode (8) with said upper AlGaAs layer (20) being on the same level with the interface between said upper InP layer (12) and said upper AlGaAs layer (20).
Claim 29
Dependent Claim
155 words
A semiconductor device including a plurality of III-V compound semiconductor layers successively disposed on a surface of a III-V compound semiconductor substrate (14), characterized by: a laminated structure comprising a lower InP layer (6), a lower AlGaAs layer (20), an upper InP layer (12), and an upper AlGaAs layer (21); a field effect transistor including a gate electrode (8) being in contact with said lower InP layer (6), the contact surface of said gate electrode (8) with said lower InP layer (6) being on the same level with the interface between said lower AlGaAs layer (20) and said lower InP layer (6); and a field effect transistor including a gate electrode (8) being in contact with said upper InP layer (12), the contact surface of said gate electrode (8) with said upper InP layer (12) being on the same level with the interface between said upper AlGaAs layer (21) and said upper InP layer (12).
Claim 30
Dependent Claim
87 words
A heterojunction bipolar transistor including a plurality of III-V compound semiconductor layers successively disposed on a surface of a III-V compound semiconductor substrate, characterized by: a laminated structure comprising, from below, a GaAs layer (111), an InP layer (102), and an AlGaAs layer (113); base electrodes (106) being in contact with said GaAs layer (111); and the contact surface of said base electrodes (106) with said GaAs layer (111) being on the same level with the interface between said InP layer (102) and said GaAs layer (111).
Claim 31
Dependent Claim
87 words
A heterojunction bipolar transistor including a plurality of III-V compound semiconductor layers successively disposed on a surface of a III-V compound semiconductor substrate, characterized by: a laminated structure comprising, from below, a GaAs layer (111), an InP layer (115), and an AlGaAs layer (113); base electrodes (106) being in contact with said InP layer (115); and the contact surface of said base electrodes (106) with said InP layer (115) being on the same level with the interface between said AlGaAs layer (113) and said InP layer (115).
References Cited (Backward Citations)
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