Heterojunction bipolar transistor

Claim 1

A heterojunction bipolar transistor formed on a principal surface of a single-crystalline silicon substrate portion of a first conductivity type, said transistor comprising: a substantially undoped silicon region contactingly overlying at least a portion of the principal surface; a silicon subcollector region of a second conductivity type opposite to the first conductivity type, the subcollector region contactingly overlying at least a portion of the substantially undoped region; a silicon collector region of the second conductivity type contactingly overlying at least a portion of the subcollector region; a base region of the first conductivity type contactingly overlying at least a portion of the collector region and forming a pn junction therewith; and a silicon emitter region of the second conductivity type which forms a pn junction with the base region, the emitter region overlying a first portion of the base region, to be referred to as the "intrinsic base," and not overlying a second portion of the base region, to be referred to as the "extrinsic base," CHARACTERIZED IN THAT a) the intrinsic base comprises a single-crystalline silicon-germanium alloy having a germanium mole fraction which is at least about 0.1 and not more than about 0.5; b) the intrinsic base is not more than about 500 Å thick; and c) a portion of the extrinsic base abuts and directly contacts the emitter region along an interface disposed substantially perpendicular to the principal surface.

Claim 3

A method for forming a heterojunction bipolar transistor on a principal surface of a portion of a single-crystalline silicon substrate, said substrate portion having a first conductivity type, the method comprising the steps of: a) growing a first, substantially undoped silicon layer on the principal surface by vapor-phase epitaxy; b) implanting ions into at least an upper portion of the first layer, said upper portion to be referred to as the "subcollector layer," such that a second conductivity type opposite to the first conductivity type is imparted to said subcollector layer; c) growing a second silicon layer, to be referred to as the "collector layer," on the subcollector layer by vapor-phase epitaxy; d) growing a layer of silicon-germanium alloy, to be referred to as the "base layer," over the collector layer by vapor-phase epitaxy; e) growing a third silicon layer, to be referred to as the "emitter layer," on the base layer by vapor-phase epitaxy; f) implanting ions into an upper portion of the emitter layer, said upper portion to be referred to as the "emitter contact layer," such that conductivity of the second type is imparted to said emitter contact layer; and g) completing the formation of the transistor; CHARACTERIZED IN THAI the method further comprises the steps of: h) after (c) and before (d), growing a fourth silicon layer between the collector and base layers by vapor-phase epitaxy; i) after (f), defining, in the fourth silicon layer, the base layer, the emitter layer, and the emitter contact layer a central region and a peripheral region such that the central regions are substantially vertically aligned and of substantially the same lateral extent; j) after (i), implanting ions in each of said peripheral regions such that implanted ions are substantially excluded from each of said central regions and conductivity of the first type is imparted to each of said peripheral regions, said implantation step resulting, in the completed transistor, in an abutment between the peripheral region of the emitter layer and the central emitter region; and k) after (j), removing the peripheral portion of the emitter contact layer.