An extendable multiple image-buffer for graphics systems

Claim 2

A graphics buffer as set forth in claim 1, wherein said bus includes: a first plurality of signal lines for conveying pixel addresses; a second plurality of signal lines for conveying pixel data, wherein said second plurality of signal lines preferably comprises a plurality of data buses, whereby at least one of said plurality of data buses preferably is coupled in common to each of said first one, said third one, and said fourth one of said modules; and a third plurality of signal lines for conveying other information, the other information being descriptive in part of the operation of said bus, whereby said third plurality of signal lines preferably comprises a control bus, said control bus preferably comprising: a signal for indicating, when asserted, that a memory refresh operation is to occur on modules having a memory comprised of dynamic memory devices.

Claim 3

A graphics buffer as set forth in claim 2 wherein said first plurality of signal lines is coupled in common to each of said first one, said second one, said third one, and said fourth one of said modules for being driven by one of said modules with an address of a pixel, the address being referenced to a coordinate system associated with the display means.

Claim 4

A graphics buffer as set forth in claim 2 or 3, wherein said third plurality of signal lines includes: a Pixel Result Bus comprised of a plurality of signal lines, individual ones of said plurality of signal lines being coupled to one of said modules for being driven thereby in accordance with a result of a pixel test performed by the module, each of said plurality of signal lines being received by others of said modules and coupled to decision means of said other modules for determining if the information stored within the associated memory is to be modified, the determination being made in accordance with the pixel test results received from all of said modules.

Claim 5

A graphics buffer according to any one of the claims 2 to 4, wherein said third plurality of signal lines includes a control bus, including: a signal line for conveying a synchronizing clock signal, the clock signal having a period defining bus cycles; a signal line for indicating, when asserted, that there is new pixel information on the bus; a signal line for indicating, when asserted, that at least one of the modules requires one or more additional bus cycles to complete an operation; and a signal line conveying a repetitive signal for sequencing all of said modules through a plurality of operational steps during the processing of pixel information for each pixel.

Claim 6

A graphics buffer for storing information describing a plurality of pixels, comprising: a plurality of modules coupled together by a bus, at least two of said modules each including memory means for storing information specifying, for each pixel of a display means, a characteristic of the pixel, said at least two of said modules each including processing means coupled to the associated memory means for modifying the information stored within the memory means; wherein said bus includes: a first plurality of signal lines for conveying pixel addresses; a second plurality of signal lines for conveying pixel data; and a third plurality of signal lines for conveying information descriptive of test results performed on pixels.

Claim 7

A graphics buffer as set forth in claim 6, wherein: said at least two of said modules each includes means for generating a plurality of consecutive processing states to accomplish a pixel processing operation, the processing states including: a Generate Address (GA) state wherein, if enabled, a pixel address is driven to the first plurality of signal lines; a Modify Address (MA) state wherein a pixel address is read from the first plurality of signal lines, and wherein the pixel address is modified, if required, to accomplish a pixel processing operation; a Read (RD) state employing the pixel address or the modified pixel address to read data from the associated memory means and, if enabled, to drive the data to the second plurality of signal lines; a Test & Compute (TC) state wherein at least one of the modules reads the data from the second plurality of signal lines and performs, if enabled, an operation on the data read from the associated memory means, each of the modules also performing a comparison operation on the data read from the associated memory means, the result of the comparison operation being driven to an associated one of the third plurality of signal lines by each of the modules; a Decide & Modify (DM) state wherein each of the module reads the third plurality of signal lines and, based on the comparison results driven thereto by other modules during the Test & Compute state, determines whether a result of the operation performed during the Test & Compute state is to be written into the associated memory means; and a Write (WR) state wherein, if enabled by the Decide & Modify state, a value computed during the Test & Compute state is written into the associated memory means at the pixel address or at the modified pixel address, whereby said generating means preferably is responsive to a pixel processing operation that performs indirect addressing to generate at least one additional MA state after the RD state and an additional RD state after the at least one additional MA state.

Claim 8

A graphics buffer for use with display means that displays n by m pixels, said graphics buffer comprising a plurality of Modules, one of said Modules comprising: means for coupling said Module to other Modules over a common bus, said Module preferably comprising means, having inputs coupled to Result signal lines generated by all Modules and responsive to the test results expressed thereon, for enabling or disabling the storing of said modified pixel information back into said memory means, whereby said enabling or disabling means preferably comprises a lookup table means having address inputs coupled to said Result signal lines, said graphics buffer preferably further comprising means for coupling said lookup table means to a Host data processing means such that the Host data processing means is enabled to load said lookup table means with predetermined information for controlling the enabling and disabling of the storing of said modified pixel information; memory means having at least (nxm) locations for storing pixel information; processor means coupled to said memory means for reading out stored pixel information therefrom, for modifying the pixel information, and for storing the modified pixel information back into said memory means; and test means coupled to said memory means for testing pixel information read therefrom and having at least one output for expressing a result of the test, said at least one output being coupled to at least one Result signal line of said common bus for reception by others of said Modules, whereby said Module preferably further comprises Address Manager means, coupled to said common bus, for receiving a pixel address therefrom and for providing the pixel address to said memory means for addressing said memory means to read out stored pixel information from one of said (nxm) locations, and whereby said Address Manager means preferably further comprises means for modifying the received pixel address before providing the received pixel address to said memory means and wherein said modifying means preferably comprises means for adding a predetermined offset to the address; said graphics buffer preferably further comprising Buffer means coupled to said common bus for inputting pixel information thereto and/or Buffer means coupled to said common bus for outputting pixel information therefrom, and wherein the functionality of at least one of said modules preferably is implemented by the operation of data processing means that is external to said graphics buffer.

Claim 9

A graphics buffer as set forth in claim 8, wherein said Address Manager means comprises means, responsive to a command provided to a selected one of said Modules, for generating a pixel address and for providing the generated pixel address to said memory means, said Address Manager means further being coupled to said common bus for providing the generated pixel address thereto for reception by non-selected ones of said Modules.

Claim 10

A graphics buffer as set forth in claim 8 or 9, wherein said Module includes sequencing means having an input coupled to a sequencing signal line of said common bus for being driven thereby through a plurality of sequential pixel processing states, whereby said sequencing means preferably comprising means for overlapping pixel processing states for simultaneously processing two or more pixels.

Claim 11

A graphics buffer as set forth in claim 10, wherein said common bus includes: a first plurality of signal lines for conveying pixel addresses; a second plurality of signal lines for conveying pixel data; and a third plurality of signal lines for conveying information descriptive of the operation of said common bus; and wherein said pixel processing states include: a Generate Address (GA) state wherein, if enabled, a pixel address is driven to the first plurality of signal lines from said Address Manager means; a Modify Address (MA) state wherein a pixel address is read from the first plurality of signal lines, and wherein the pixel address is modified, if required, to accomplish a pixel processing operation; a Read (RD) state wherein the pixel address or the modified pixel address is employed to read data from the memory means and, if enabled, the data read from the memory means is driven to the second plurality of signal lines; a Test & Compute (TC) state wherein the Module reads the data from the second plurality of signal lines and wherein the test means compares the data read from the second plurality of signal lines to the data read from the memory means, wherein the processor means computes a revised data value from the data read from the memory means, and wherein the test means outputs the result of the comparison operation to the associated one or more Result signal lines; a Decide & Modify (DM) state wherein the Module reads all of the Result signal lines and, based on the results output thereto during the Test & Compute state, determines whether the revised data value computed during the Test & Compute state is to be written into the memory means; and a Write (WR) state wherein, if enabled by the Decide & Modify state, the revised data value computed during the Test & Compute state is written into the memory means at the pixel address or at the modified pixel address, whereby said sequencing means preferably is responsive to a pixel processing operation that performs indirect addressing so as to generate at least one additional MA state after the RD state and an additional RD state after each additional MA state.

Claim 12

A graphics buffer according to any one of the claims 8 to 11, wherein said Address Manager means comprises register means for storing coordinates that define a two-dimensional pixel region of the display means, whereby said Address Manager means preferably further comprises means for loading said registers with addresses received from said common bus, and whereby said Address Manager means preferably further comprises means, responsive to information stored within said register means, for generating addresses that lie within the two-dimensional pixel region, said graphics buffer preferably further comprising means for storing within said register means coordinates that define a two- dimensional pixel region of the display means corresponding to modified pixels that are stored back into said memory means.

Claim 13

A graphics buffer according to any one of the claims 8 to 12 and further including means for specifying a corner of the two-dimensional pixel region at which to begin the generation of addresses.

Claim 14

A graphics buffer according to any one of the claims 8 to 13, wherein said common bus includes at least one data bus, wherein said processor means includes an operand register means, and wherein said processor means is responsive to an operation code stored within an operation register means for performing an arithmetic or a logical operation on (a) the output of said memory means and on data received from said at least one data bus, or (b) on the output of said memory means and on data stored within said operand register means, or (c) on data stored within said operand register means and on data received from said at least one data bus, whereby said operand register means preferably is coupled to a Host data processor means for being loaded thereby with an operand and/or an operation code.

Claim 15

A graphics buffer according to any one of the claims 8 to 14, wherein said common bus includes at least one data bus, wherein said processor means includes an operand register means, and wherein said processor means is responsive to an operation code for performing an arithmetic or a logical operation on the output of said memory means and on data stored within said operand register means, and wherein said operation code is provided from an output of said enabling or disabling means.

Claim 16

A graphics buffer according to any one of the claims 8 to 15, wherein said processor means includes a writemask register means having an output for specifying one or more bits of the output of said memory means that are not to be affected by the operation of said processing means.

Claim 17

A graphics buffer according to any one of the claims 8 to 16, wherein said common bus includes at least one data bus, and wherein said test means includes a reference register means, and wherein said test means is responsive to a test specifier stored within a test register means for comparing (a) the output of said memory means to data appearing on said at least one data bus, or (b) an output of the reference register means to the output of said memory means or to the data appearing on said at least one data bus, whereby said test means preferably comprises means for adding a content of said reference register means to the output of said memory means prior to the comparison of said output of said memory means to the data appearing on said at least one data bus and/or means for specifying bits that are to be compared one to another.

Claim 18

A graphics buffer according to any one of the claims 8 to 17, wherein said third plurality of signal lines include: a signal line for conveying a synchronizing clock signal, the clock signal having a period defining bus cycles; a signal line for indicating, when asserted, that there is new pixel information on the bus; and a signal line for indicating, when asserted, that at least one of the modules requires one or more additional bus cycles to complete an operation.

Claim 19

A graphics buffer according to any one of the claims 8 to 18, wherein said third plurality of signal lines includes: a signal for indicating, when asserted, that a memory refresh operation is to occur on Modules having a memory means comprised of dynamic memory devices.

Claim 20

A graphics system comprising: means for generating a plurality of graphics primitives; means for transforming the graphics primitives into a plurality of pixels, each pixel being described by a pixel address and pixel data; display means that displays n by m pixels; and graphics buffer means for receiving the pixels from the transforming means and for providing pixels to said display means, wherein said graphics buffer means includes a plurality of Modules, one of said Modules comprising: means for coupling said Module to other Modules over a common bus; memory means having at least (nxm) locations for storing pixel data; processor means coupled to said memory means for reading out stored pixel data therefrom, for modifying the pixel data, and for storing the modified pixel data back into said memory means; and test means coupled to said memory means for testing pixel data read therefrom and having at least one output for expressing a result of the test, said at least one output being coupled to at least one Result signal line of said common bus for reception by others of said Modules.

Claim 21

A graphics system as set forth in claim 20, wherein said common bus includes: a first plurality of signal lines for conveying pixel addresses; a second plurality of signal lines for conveying pixel data; and a third plurality of signal lines for conveying information descriptive of the operation of said common bus.

Claim 22

A graphics system as set forth in claim 21, wherein said third plurality of signal lines include: a signal line for conveying a synchronizing clock signal, the clock signal having a period defining bus cycles; a signal line for indicating, when asserted, that there is new pixel data on the second plurality of signal lines; and a signal line for indicating, when asserted, that at least one of the modules requires one or more additional bus cycles to complete an operation.