Patent EP0547640A2 successfully refreshed from Google Patents.
EP0547640A2
Expired / Lapsed
EP
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Non-volatile semiconductor memory device and memory system using the same
Assignee: Toshiba Corp
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Filing: 1992-12-21
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Granted: —
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Expires: 2012-12-21
Abstract
Abstract The time required for the program verify and erase verify operations can be shortened. The change of threshold values of memory cells can be suppressed even if the write and erase operations are executed repetitively. After the program and erase operations, whether the operations were properly executed can be judged simultaneously for all bit lines (BL) basing upon a change, after the pre-charge, of the potential at each bit line (BL), without changing the column address. In the data rewrite operation, the rewrite operation is not effected for a memory cell with the data once properly written, by changing the data in the data register (DR).
Inventors
- 👤 Tomoharu Tanaka
- 👤 Hideo Kato
- 👤 Hiroto Nakai
- 👤 Yoshiyuki Tanaka
- 👤 Riichiro Shirota
- 👤 Seiichi Aritome
- 👤 Yasuo Itoh
- 👤 Yoshihisa Iwata
- 👤 Hiroshi Nakamura
- 👤 Hideko Odaira
- 👤 Yutaka Okamoto
- 👤 Masamichi Asano
- 👤 Kaoru Tokushige
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-05 03:46
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/70; G11C29/78; G11C29/785; G11C16/00; G11C16/02; G11C16/06; G06; G06F; G06F11/00; G06F11/07; G06F11/08; G06F11/10; G06F11/1008; G11C16/10; G11C16/12; G11C16/24; G11C16/34; G11C16/3436; G11C16/344; G11C16/3454; G11C29/04; G11C29/08; G11C29/12; G11C29/18; G11C29/30; G11C29/34; G11C29/52; G06F11/1068; G06F2201/00; G06F2201/81; G06F2212/00; G06F2212/20; G06F2212/202; G06F2212/2022
Claims Analysis
Total Claims: 26
Claim 1
Independent Claim
152 words
A non-volatile semiconductor memory device, comprising: a plurality of data latch means (IV1, IV2) for temporarily storing write data; a plurality of memory cells provided for each of said plurality of data latch means (IV1, IV2), a write operation for each said memory cell being executed in accordance with the data stored in the corresponding one of said plurality of data latch means; a plurality of comparator means (T11, T12, TT) each provided for each of said plurality of data latch means (TV1, TV2), each of said plurality of comparator means comparing, sequentially after said write operation, said data stored in said corresponding data latch means with the data read from said memory cell, and judging whether data was written in said memory cell; and simultaneous detecting means (BBC) for outputting a write completion signal when all of said plurality of comparator means judge that data were written in corresponding memory cells.
Claim 2
Dependent Claim
249 words
A non-volatile semiconductor memory device, comprising: a plurality of data latch means (IV1, IV2) for temporarily storing write data at first or second logical levels; a plurality of memory cells each provided for each of said plurality of data latch means (IV1, IV2), data being stored in each of said plurality of memory cells in an erase state when the threshold voltage of each said memory cell is within a first range and in a write state when the threshold voltage of each said memory cell is within a second range, and in a write operation, said threshold voltage being shifted when said first logical level is stored in each said data latch means and a shift of said threshold voltage being suppressed when said second logical level is stored in each said data latch means; a plurality of data resetting means (T11, T12, TT) each provided for each of said plurality of data latch means (TV1, TV2), each of said plurality of data setting means comparing, sequentially in a verify operation after said write operation, said data stored in each said data latch means with the data read from each said memory cell, and resetting said second logical level to each said data latch means (TV1, TV2) when the threshold voltage of each said memory cell enters said second range; simultaneous detecting means (BBC) for outputting a write completion signal when said second logical level was reset to all of said plurality of data latch means (IV1, IV2).
Claim 3
Dependent Claim
56 words
A non-volatile semiconductor memory device according to claim 2, wherein said data latch means (TV1, TV2) is a flip-flop circuit, and said simultaneous detecting means includes a plurality of data detector MOS transistors (T14) each having a gate connected to one end of said flip-flop circuit, said data detector MOS transistors (T14) being connected in parallel.
Claim 4
Dependent Claim
33 words
A non-volatile semiconductor memory device according to claim 3, including breaker means provided for each said data detector MOS transistor (T14) for inhibiting flow of current through said data detector MOS transistor (T14).
Claim 5
Dependent Claim
56 words
A non-volatile semiconductor memory device according to claim 2, wherein said data latch means (TV1, TV2) is a flip-flop circuit, and said simultaneous detecting means includes a plurality of data detector MOS transistors (QnDi) each having a gate connected to one end of said flip-flop circuit, said data detector MOS transistors (QnDi) being connected in series.
Claim 6
Dependent Claim
358 words
A non-volatile semiconductor memory device, comprising: a plurality of data latch means (IV1, IV2) for temporarily storing inputted write data at first or second logical levels; a plurality of memory cells each provided for each of said plurality of data latch means (IV1, IV2), data being stored in each of said plurality of memory cells in an erased state when the threshold voltage of each said memory cell is within a first range and as a write state when the threshold voltage of each said memory cell is within a second range, in a write operation said threshold voltage being shifted from said first range toward said second range when said first logical level is stored in each said data latch means and a shift of said threshold voltage being suppressed when said second logical level is stored in each said data latch means, and in an erase operation said threshold voltage being shifted in an opposite manner to said write operation; a plurality of data resetting means (T11, T12, TT) each provided for each of said plurality of data latch means (TV1, TV2), each of said plurality of data resetting means comparing, in a write verify operation executed after said write operation, said data stored in each said data latch means with the data read from each said memory cell, and resetting said second logical level to each said data latch means (TV1, TV2) when the threshold voltage of each said memory cell enters said second range, and in an erase verify operation executed after said erase operation, setting to each said data latch means (TV1, TV2) said second logical level when said threshold voltage of each said memory cell is within said second range, and said first logical level when said threshold voltage of each said memory cell is within said first range; and simultaneous detecting means (BBC) for outputting a write completion signal when said second logical level was set to all of said plurality of data latch means (IV1, IV2), and outputting an erase completion signal when said first logical level was set to all of said plurality of data latch means (IV1, IV2).
Claim 7
Dependent Claim
77 words
A non-volatile semiconductor memory device according to claim 6, wherein said data latch means (TV1, TV2) is a flip-flop circuit, and said simultaneous detecting means (BBC) includes a plurality of data detector MOS transistors (T14) each having a gate connected via a first transistor (T PV ) to one end, and via a second transistor (T EV ) to the other end, respectively of said flip-flop circuit, said data detector MOS transistors (T14) being connected in parallel.
Claim 8
Dependent Claim
77 words
A non-volatile semiconductor memory device according to claim 6, wherein said data latch means (TV1, TV2) is a flip-flop circuit, and said simultaneous detecting means (BBC) includes a plurality of data detector MOS transistors (QnDi) each having a gate connected via a first transistor (T PV ) to one end, and via a second transistor (T EV ) to the other end, respectively of said flip-flop circuit, said data detector MOS transistors (QnDi) being connected in series.
Claim 9
Dependent Claim
41 words
A non-volatile semiconductor memory device according to claim claim 2 or 6, further including write operation control means for controlling to repetitively execute said write operation and said verify operation until said simultaneous detecting means (BBC) outputs said write completion signal.
Claim 10
Dependent Claim
55 words
A non-volatile semiconductor memory device according to claim 9, further including latch data output means for outputting data of said plurality of data latch means when said simultaneous detecting means (BBC) does not output said write completion signal after said write operation control means has repetitively controlled said write operation and said simultaneous detecting operation.
Claim 11
Dependent Claim
41 words
A non-volatile semiconductor memory device according to claim 6 or 7, further including erase operation control means for controlling to repetitively execute said erase operation and said simultaneous detecting operation until said simultaneous detecting means (BBC) outputs said erase completion signal.
Claim 12
Dependent Claim
55 words
A non-volatile semiconductor memory device according to claim 11, further including latch data output means for outputting data of said plurality of data latch means when said simultaneous detecting means (BBC) does not output said erase completion signal after said erase operation control means has repetitively controlled said erase operation and said simultaneous detecting operation.
Claim 13
Dependent Claim
29 words
A non-volatile semiconductor memory device according to claim 1, 2 or 6, further including output means for outputting one of said write completion signal and said erase completion signal.
Claim 14
Dependent Claim
183 words
A memory system, comprising: a plurality of data latch means (IV1, IV2) for temporarily storing write data; a plurality of memory cells each provided for each of said plurality of data latch means (IV1, IV2), a write operation for each said memory cell being executed in accordance with the data stored in a corresponding one of said plurality of data latch means; a plurality of comparator means (T11, T12, TT) each provided for each of said plurality of data latch means (TV1, TV2), each of said plurality of comparator means comparing, sequentially after said write operation, said data stored in said corresponding one of said plurality of data latch means with data read from said memory cell, and judging whether data was written in said memory cell; simultaneous detecting means (BBC) for outputting a write completion signal (VFY) when all of said plurality of comparator means judge that data was written in corresponding memory cells; and write data control means (122) for transferring new write data to said data latch means when said simultaneous detecting means (BBC) outputs said write completion signal (VFY).
Claim 15
Dependent Claim
274 words
A memory system, comprising: a plurality of data latch means (IV1, IV2) for temporarily storing write data at first and second logical levels; a plurality of memory cells each provided for each of said plurality of data latch means (IV1, IV2), data being stored in each of said plurality of memory cells in an erase state when the threshold voltage of each said memory cell is within a first range and in a write state when the threshold voltage of each said memory cell is within a second range, in a write operation said threshold voltage being shifted when said first logical level is stored in each said data latch means (IV1, IV2) and a shift of said threshold voltage being suppressed when said second logical level is stored in each said data latch means (IV1, IV2); a plurality of data setting means (T11, T12, TT) each provided for each of said plurality of data latch means (TV1, TV2), each of said plurality of data setting means comparing, sequentialy after said write operation, said data stored in each said data latch means with data read from each said memory cell, and resetting said second logical level to each said data latch means (TV1, TV2) when the threshold voltage of each said memory cell enters said second range; simultaneous detecting means (BBC) for outputting a write completion signal (VFY) when said second logical level was set to all of said plurality of data latch means (IV1, IV2); and write data control means (122) for transferring new write data to said data latch means when said simultaneous detecting means (BBC) outputs said write completion signal (VFY).
Claim 16
Dependent Claim
62 words
A non-volatile semiconductor memory device according to claim 1, 2 or 6, wherein said plurality of memory cells are divided into a certain number of groups and the memory cells in each group are connected in series to constitute a NAND cell (BC), at least one said NAND cell being provided for each of said plurality of data latch means (IV1, IV2).
Claim 17
Dependent Claim
59 words
A memory system according to claim 14 or 15, wherein said plurality of memory cells are divided into a certain number of groups and the memory cells in each group are connected in series to constitute a NAND cell (BC), at least one said NAND cell being provided for each of said plurality of data latch means (IV1, IV2).
Claim 18
Dependent Claim
90 words
A non-volatile semiconductor memory device according to claim 1, wherein each said comparator means (T11, T12, TT) has a first terminal connected to each said memory cell and a second terminal connected to each said data latch means (IV1, IV2), first switching means (T12) and second switching mean (T11) are connected in series between said first terminal and a predetermined level (BLCRL), said first switching means (T12) being turned on upon said verify operation, and a control terminal of said second switching means (T11) is connected to said second terminal.
Claim 19
Dependent Claim
90 words
A memory system according to claim 14, wherein each said comparator means (T11, T12, TT) has a first terminal connected to each said memory cell and a second terminal connected to each said data latch means (IV1, IV2), first switching means (T12) and second switching mean (T11) are connected in series between said first terminal and a predetermined level (BLCRL), said first switching means (T12) being turned on upon execution of said verify operation, and a control terminal of said second switching means (T11) is connected to said second terminal.
Claim 20
Dependent Claim
94 words
A non-volatile semiconductor memory device according to claim 2 or 6, wherein said data resetting means (T11, T12, TT) has a first terminal connected to each said memory cell and a second terminal connected to each said data latch means (IV1, IV2), first switching means (T12) and second switching means (T11) are connected in series between said first terminal and a predetermined level (BLCRL), said first switching means (T12) being turned on upon execution of said verify operation, and a control terminal of said second switching means (T11) is connected to said second terminal.
Claim 21
Dependent Claim
90 words
A memory system according to claim 15, wherein said data resetting means (T11, T12, TT) has a first terminal connected to each said memory cell and a second terminal connected to each said data latch means (IV1, IV2), first switching means (T12) and second switching means (T11) are connected in series between said first terminal and a predetermined level (BLCRL), said first switching means (T12) being turned on upon execution of said verify operation, and a control terminal of said second switching means (T11) is connected to said second terminal.
Claim 22
Dependent Claim
42 words
A non-volatile semiconductor memory device according to claim 3 or 7, wherein switching means (TP₁) capable of turning on/off upon execution of a verify read operation is connected between a common connection point of said plurality of data detector MOS transistors (T14).
Claim 23
Dependent Claim
55 words
A non-volatile semiconductor memory device according to claim 1, 2 or 6, further comprising an output buffer for receiving an output from said simultaneous detecting means (BBC) and data read from each said memory cell, and selectively outputting one of said output from said simultaneous detecting means and data read from each said memory cell.
Claim 24
Dependent Claim
87 words
A non-volatile semiconductor memory device according to claim 1, 2 or 6, further comprising: a plurality of bit lines (BLai, BLbi) for transferring data read from each memory cell; and sense means (FF) for sensing said data read from said bit lines, wherein said sense means (FF) has two input ends, compares a signal applied to one end with a reference potential applied to the other end, and outputs the comparison result, said two input ends being connected to different ones of said bit lines (BLai, BLbi).
Claim 25
Dependent Claim
84 words
A memory system according to claim 14 or 15, further comprising: a plurality of bit lines (BLai, BLbi) for transferring data read from each memory cell; and sense means (FF) For sensing said data read from said bit lines, wherein said sense means (FF) has two input ends, compares a signal applied to one end with a reference potential applied to the other end, and outputs the comparison result, said two input ends being connected to different ones of said bit lines (BLai, BLbi).
Claim 26
Dependent Claim
58 words
A memory system according to claim 22, further comprising fuse means (Fu1, Fu2) capable of inhibiting a flow of current at least at one of two points between said common connection point and one end of each said data detector MSO transistor and between the other end of each said data detector MOS transistor and said power supply.
References Cited (Backward Citations)
No citation records indexed.
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