Patent EP0544338A1 successfully refreshed from Google Patents.
EP0544338A1
Expired / Lapsed
EP
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MOS operational amplifier circuit
Assignee: Oki Electric Industry Co Ltd
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Filing: 1992-11-27
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Granted: —
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Expires: 2012-11-27
Abstract
Abstract An operational amplifier circuit is composed of a differential amplifier circuit for delivering a signal which is obtained by amplifying a difference between voltage levels of two signals; a level shift circuit for shifting and delivering the voltage level of the signal delivered from the differential amplifier circuit; a first amplifier circuit for amplifying and delivering the signal from the level shift circuit; and a second amplifier circuit for amplifying and delivering the voltage level of the signal delivered from the differential amplifier circuit, and a CMOS output circuit whose conductive state is controlled in accordance with voltage levels of the signals delivered from the first and second amplifier circuits.
Inventors
- 👤 Seiji c/o Oki Electric Ind. Co. Ltd. Okamoto
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-23 15:46
CPC Classifications
H; H03; H03F; H03F3/00; H03F3/45; H03F3/45071; H03F3/45076; H03F3/45179; H03F3/30; H03F3/3001; H03F2200/00; H03F2200/153; H03F2203/00; H03F2203/30; H03F2203/30006; H03F2203/30018; H03F2203/45; H03F2203/45224; H03F2203/45274
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
452 words
An operational amplifier circuit composed of MOS FETs comprising: a differential amplifier circuit having first and second input terminals and a first output node, for delivering a signal having a voltage level proportional to a difference between a voltage level of a signal applied to sad first input terminal and a voltage level of a signal applied to said second input terminal, to said first output node, said operational amplifier being adapted to deliver a first signal having a first voltage level when the voltage level of the signal applied to said first input terminal is higher than the voltage level of the signal applied to said second input terminal, and to deliver a second signal having a second voltage level when the voltage level of the signal applied to the first input terminal is lower than the voltage level of the signal applied to the second input terminal; a level shift circuit connected to said first output node, for delivering a third signal which is obtained by shifting the voltage level of said first signal in a direction of the first voltage level in response to said first signal, and delivering a fourth signal which is obtained by shifting the voltage level of said second signal in a direction of the second voltage level in response to the second signal; a first amplifier circuit connected to said level shift circuit, for delivering a fifth signal having the third voltage level in response to said third signal, and delivering a sixth signal having the fourth voltage level in response to said fourth signal; a second amplifier circuit connected to said first output node, for delivering a seventh signal having the fifth voltage level in response to said first signal, and delivering an eighth signal having the sixth voltage level in response to said second signal; an output circuit connected to said first and second amplifier circuits, a first voltage source having the first voltage level, and a second voltage source having the second voltage level, and having first and second conductive MOS transistors which are connected between said first and second voltage sources in series with a second output node being interposed between said first and second conductive MOS transistors, said rust conductive MOS transistor being adapted to be completely turned on in response to said fifth signal, but to be incompletely turned on in response to said sixth signal, and said second conductive MOS transistor being adapted to completely turned on in response to said eighth signal but be incompletely turned on in response to said seventh signal; and an output terminal connected to said second output node for receiving a signal having the voltage level of said first input terminal.
Claim 2
Dependent Claim
452 words
An operational amplifier circuit composed of MOS FETs comprising: a differential amplifier circuit having first and second input terminals and a first output node, for delivering a signal having a voltage level proportional to a difference between a voltage level of a signal applied to sad first input terminal and a voltage level of a signal applied to said second input terminal, to said first output node, said operational amplifier being adapted to deliver a first signal having a first voltage level when the voltage level of the signal applied to said first input terminal is higher than the voltage level of the signal applied to said second input terminal, and to deliver a second signal having a second voltage level when the voltage level of the signal applied to the first input terminal is lower than the voltage level of the signal applied to the second input terminal; a level shift circuit connected to said first output node, for delivering a third signal which is obtained by shifting the voltage level of said first signal in a direction of the first voltage level in response to said first signal, and delivering a fourth signal which is obtained by shifting the voltage level of said second signal in a direction of the second voltage level in response to the second signal; a first amplifier circuit connected to said level shift circuit, for delivering a fifth signal having the third voltage level in response to said third signal, and delivering a sixth signal having the fourth voltage level in response to said fourth signal; a second amplifier circuit connected to said first output node, for delivering a seventh signal having the fifth voltage level in response to said first signal, and delivering an eighth signal having the sixth voltage level in response to said second signal; an output circuit connected to said first and second amplifier circuits, a first voltage source having the first voltage level, and a second voltage source having the second voltage level, and having first and second conductive MOS transistors which are connected between said first and second voltage sources in series with a second output node being interposed between said first and second conductive MOS transistors, said rust conductive MOS transistor being adapted to be completely turned on in response to said fifth signal, but to be incompletely turned on in response to said sixth signal, and said second conductive MOS transistor being adapted to completely turned on in response to said eighth signal but be incompletely turned on in response to said seventh signal; and an output terminal connected to said second output node for receiving a signal having the voltage level of said first input terminal.
Claim 3
Dependent Claim
30 words
An operational amplifier circuit as set forth in claim 1, wherein said first conductive MOS transistor is a PMOS transistor, and said second conductive MOS transistor is an NMOS transistor.
Claim 4
Dependent Claim
101 words
An operational amplifier circuit as set forth in claim 1, wherein said level shift circuit comprises a first NOMOS transistor circuit having a drain connected said first voltage source, a gate connected said first output node and a source connected to said first amplifier circuit, and a second NMOS transistor having a source connected to said second voltage source, a gate connected to a bias terminal to which a bias voltage is applied, and a drain connected to the source of said first NMOS transistor, and said third and fourth signal are delivered from the source of said first NMOS transistor.
Claim 5
Dependent Claim
91 words
An operational amplifier circuit as set forth in claim 1, wherein said first amplifier circuit comprises a first PMOS transistor having a source connected said first voltage source, a gate and a drain connected commonly to said output circuit, and a third NMOS transistor having a source connected to said second voltage source, a gate connected to said level shift circuit and a drain connected to the drain of said first PMOS transistor, and said fifth signal and said sixth signal are delivered from the drain of said first PMOS transistor.
Claim 6
Dependent Claim
91 words
An operational amplifier circuit as set forth in claim 1, wherein said second amplifier circuit comprises a second PMOS transistor having a source connected to said first voltage source, a drain connected to said output circuit and a gate connected to said first output node, and a fourth NMOS transistor having a source connected to said second voltage source, and a gate and a drain connected commonly to the drain of said second PMOS transistor, and said seventh or eighth signal is delivered from the drain of said second PMOS transistor.
Claim 7
Dependent Claim
36 words
An operational amplifier circuit as set forth in claim 4, wherein said first PMOS transistor has a threshold voltage which is equal to a threshold voltage of said first conductive MOS transistor in said output circuit.
Claim 8
Dependent Claim
36 words
An operational amplifier circuit as set forth in claim 5, wherein said fourth NMOS transistor has a threshold voltage which is equal to a threshold voltage of said second conductive MOS transistor in said output circuit.
Claim 9
Dependent Claim
46 words
An operational amplifier circuit as set forth in claim 4, wherein said fifth signal has said third voltage level, and said sixth signal has said fourth voltage level which is shifted from said first voltage level by the threshold voltage level of said first PMOS transistor.
Claim 10
Dependent Claim
49 words
An operational amplifier circuit as set forth in claim 5, wherein said seventh signal has said fifth voltage level which is shifted from said first voltage level by a voltage near to the threshold voltage of said fourth NMOS transistor, and said eighth signal has said sixth voltage level.
Claim 11
Dependent Claim
78 words
An operational amplifier circuit as set forth in claim 1, wherein said operational amplifier circuit further comprises: a first feed-back circuit connected between said first amplifier circuit and said first output node, for feeding back the voltage level of said fifth signal to said first output node; and a second feed-back circuit connected between said second amplifier circuit and said first output node, for feeding back the voltage level of said eighth signal to said first output node.
Claim 12
Dependent Claim
233 words
An operational amplifier composed of MOS FETs comprising: a differential amplifier circuit having first and second input terminals and a first output node, for delivering a signal having a voltage level proportional to a difference between a voltage level of a signal applied to sad first input terminal and a voltage level of a signal applied to said second input terminal, to said first output node, said operational amplifier being adapted to deliver a first signal having a first voltage level when the voltage level of the signal applied to said first input terminal is higher than the voltage level of the signal applied to said second input terminal, and to deliver a second signal having a second voltage level when the voltage level of the signal applied to the first input terminal is lower than the voltage level of the signal applied to the second input terminal; a first amplifying means for amplifying said first signal and simultaneously shifting the voltage level of said first signal; a second amplifying means for amplifying said second signal; a first conductive MOS transistor whose conductive state is controlled by said first signal amplified by said first amplifying means; a second conductive MOS transistor whose conductive state is controlled by said second signal amplified by said second amplifying means; and an output terminal connected between said first conductive MOS transistor and said second conductive MOS transistor.
Claim 13
Dependent Claim
233 words
An operational amplifier composed of MOS FETs comprising: a differential amplifier circuit having first and second input terminals and a first output node, for delivering a signal having a voltage level proportional to a difference between a voltage level of a signal applied to sad first input terminal and a voltage level of a signal applied to said second input terminal, to said first output node, said operational amplifier being adapted to deliver a first signal having a first voltage level when the voltage level of the signal applied to said first input terminal is higher than the voltage level of the signal applied to said second input terminal, and to deliver a second signal having a second voltage level when the voltage level of the signal applied to the first input terminal is lower than the voltage level of the signal applied to the second input terminal; a first amplifying means for amplifying said first signal and simultaneously shifting the voltage level of said first signal; a second amplifying means for amplifying said second signal; a first conductive MOS transistor whose conductive state is controlled by said first signal amplified by said first amplifying means; a second conductive MOS transistor whose conductive state is controlled by said second signal amplified by said second amplifying means; and an output terminal connected between said first conductive MOS transistor and said second conductive MOS transistor.
Claim 14
Dependent Claim
30 words
An operational amplifier circuit as set forth in claim 12, wherein said first conductive MOS transistor is a PMOS transistor, and said second conductive MOS transistor is an NMOS transistor.
Claim 15
Dependent Claim
44 words
An operational amplifier circuit as set forth in claim 12, wherein said first signal amplified by said first amplifying means turns on said first conductive MOS transistor, and said second signal amplified by said second amplifying means turns on said second conductive MOS transistor.
References Cited (Backward Citations)
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