Patent EP0464406A2 successfully refreshed from Google Patents.
Patent EP0543361A2 successfully refreshed from Google Patents.
EP0543361A2
Expired / Lapsed
EP
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Semiconductor device and method of manufacturing the same
Assignee: Canon Inc
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Filing: 1992-11-19
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Granted: —
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Expires: 2012-11-19
Abstract
Abstract A semiconductor device having a semiconductor layer formed on a substrate having an insulating surface, comprises a first region formed by processing the semiconductor layer from one major surface thereof, and a second region formed by processing the semiconductor layer from the other major surface, the first and second regions cooperate to constitute a semiconductor function element. <IMAGE>
Inventors
- 👤 Mamoru C/O Canon Kabushiki Kaisha Miyawaki
- 👤 Yasushi C/O Canon Kabushiki Kaisha Kawasumi
- 👤 Shunsuke C/O Canon Kabushiki Kaisha Inoue
- 👤 Yutaka c/o Canon Kabushiki Kaisha Akino
- 👤 Toru C/O Canon Kabushiki Kaisha Koizumi
- 👤 Tetsunobu C/O Canon Kabushiki Kaisha Kohchi
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-07 09:52
CPC Classifications
H; H10; H10P; H10P36/00; H10P36/03; H10P36/07; H10D; H10D86/00; H10D86/201; H10P90/00; H10P90/19; H10P90/1904; H10P90/1906; H10W; H10W10/00; H10W10/01; H10W10/061; H10W10/10; H10W10/181; H10W46/00; H10D84/00; H10D84/80; H10D84/82; H10D84/83; H10D84/85; H10P90/1914; H10W10/011; H10W10/012; H10W10/014; H10W10/041; H10W10/13; H10W10/17; H10W10/40; H10W46/101; H10W46/301; H10W46/501
Claims Analysis
Total Claims: 29
Claim 1
Independent Claim
58 words
A semiconductor device having a semiconductor layer formed on a substrate having an insulating surface, comprising a first region formed by processing said semiconductor layer from one major surface thereof, and a second region formed by processing said semiconductor layer from the other major surface, wherein said first and second regions cooperate to constitute a semiconductor function element.
Claim 2
Dependent Claim
18 words
A device according to claim 1, wherein the processing of said semiconductor layer includes an impurity diffusion step.
Claim 3
Dependent Claim
17 words
A device according to claim 1, wherein the processing of said semiconductor layer includes a deposition step.
Claim 4
Dependent Claim
17 words
A device according to claim 1, wherein the processing of said semiconductor layer includes an etching step.
Claim 5
Dependent Claim
13 words
A device according to claim 1, wherein said function element is a transistor.
Claim 6
Dependent Claim
19 words
A device according to claim 1, wherein said first region is part of a collector region of a transistor.
Claim 7
Dependent Claim
19 words
A device according to claim 1, wherein said first region is part of a gate region of a transistor.
Claim 8
Dependent Claim
68 words
A semiconductor device having a semiconductor layer formed on a substrate having an insulating surface, said semiconductor layer having a plurality of semiconductor function elements, comprising: a first region formed by processing said semiconductor layer from one major surface thereof, and a second region formed by processing said semiconductor layer from the other major surface, wherein said first and second regions cooperate to constitute an element isolation region.
Claim 9
Dependent Claim
18 words
A device according to claim 8, wherein the processing of said semiconductor layer includes an insulator deposition step.
Claim 10
Dependent Claim
17 words
A device according to claim 8, wherein the processing of said semiconductor layer includes an etching step.
Claim 11
Dependent Claim
16 words
A device according to claim 8, wherein said first region also serves as an alignment mark.
Claim 12
Dependent Claim
32 words
A device according to claim 8, wherein said function element comprises a first semiconductor region formed from said one major surface and a second semiconductor region formed from said other major surface.
Claim 13
Dependent Claim
24 words
A device according to claim 12, wherein said function element is a transistor, and said first semiconductor region is part of a collector region.
Claim 14
Dependent Claim
24 words
A device according to claim 12, wherein said function element is a transistor, and said first semiconductor region is part of a gate region.
Claim 15
Dependent Claim
35 words
A device according to claim 8, wherein said element isolation region comprises a plurality of element isolation regions, some of which are constituted by one of insulating said first region and insulating said second region.
Claim 16
Dependent Claim
28 words
A device according to claim 8, wherein said first region as an insulating region is in contact with an impurity doped region processed from said other major surface.
Claim 17
Independent Claim
71 words
A method of manufacturing a semiconductor device having a semiconductor layer formed on a support having an insulating surface, comprising the steps of: forming a first region by processing said semiconductor layer from one major surface thereof; bonding said one major surface to said support; forming a second region by processing said semiconductor layer from said other major surface; and forming a semiconductor function element having said first and second regions.
Claim 18
Dependent Claim
23 words
A method according to claim 17, wherein said first region is a collector buried layer, and said second region is a base region.
Claim 19
Dependent Claim
23 words
A method according to claim 17, wherein said first region is a gate region and said second region is source and drain regions.
Claim 20
Independent Claim
71 words
A method of manufacturing a semiconductor device having a semiconductor layer formed on a support having an insulating surface, comprising the steps of: forming a first region by processing said semiconductor layer from one major surface thereof; bonding said one major surface to said support; forming a second region by processing said semiconductor layer from said other major surface; and forming an element isolation region having said first and second regions.
Claim 21
Dependent Claim
20 words
A method according to claim 20, wherein at least one of said first and second regions is an insulating region.
Claim 22
Dependent Claim
16 words
A method according to claim 20, wherein said first region also serves as an alignment mark.
Claim 23
Independent Claim
80 words
A method of manufacturing a semiconductor device, comprising the steps of: preparing a first body having a first semiconductor layer; forming an alignment mark and a first region for forming a structural body in a first surface of said first semiconductor layer; bonding said first body and a second body such that said first surface faces said second body; and performing alignment using a region serving as said alignment mark to process a second surface of said first semiconductor device.
Claim 24
Dependent Claim
16 words
A method according to claim 23, wherein said alignment mark is formed in said first surface.
Claim 25
Dependent Claim
18 words
A method according to claim 23, wherein said alignment mark is a recess formed in said first surface.
Claim 26
Dependent Claim
25 words
A method according to claim 23, wherein said alignment mark is formed in said second surface and is removed before said second surface is processed.
Claim 27
Dependent Claim
43 words
A method according to claim 23, wherein said alignment mark is formed in said second surface and is removed before said second surface is processed but after another alignment mark is formed in said second body on the basis of said alignment mark.
Claim 28
Dependent Claim
47 words
A semiconductor device having a first semiconductor layer on a substrate, wherein a region consisting of a material different from that of said first semiconductor layer for forming a structural body and an alignment mark portion are formed on a substrate-side surface of said first semiconductor layer.
Claim 29
Independent Claim
66 words
A method of manufacturing a semiconductor device in an SOI body having a heavily doped buried layer formed in a semiconductor body, wherein in mask alignment for said buried layer, a position of said buried layer is recognized by measuring a transmitted light intensity difference caused by the presence/absence of said buried layer, using light having a wavelength which can be transmitted through said SOI body.
References Cited (Backward Citations)
No citation records indexed.
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