A design method for the automatic implementation of data-flow partitions in asic's

Claim 1

A design method for the automatic implementation of data-flow partitions in semiconductor integrated circuit chips characterized in that it comprises: - a logic entry step (S1) to capture with a high level language the design of the chip, making use of the logical macrofunction library to describe data-flow and control logic partitions in a high level logic (D1); - a high level logic simulation step (S2) using word model data (D2) that represent the logic behaviour of the macrofunctions to simulate at high level the behaviour of said high level logic (D1); - a structure extraction step (S3) to extract the pertinent physical data from said high level logic (D1) using the word map D3 that describes the physical placement of the books within the macrofunctions and the logic models of the books D4 to generate a book level logic (D5), the hierarchy description (D6) which describes the relative placement within each macrofunction the sorted netlist (D7) which describes the connections between the basic elements, and the R/C estimates (D8) which contain load resistance and capacitance estimates; - a book level logic verification step (S4) to make sure that the book level logic (D5) is consistent with said high level logic (D1); - a power assignment step (S7) using said book level logic (D5), the R/C estimates (D8), and the book delay rules (D11), to set up the correct level of power of the books contained in said book level logic (D5) to generate updated data (D5a); - a timing analysis step (S8) based on said updated book level logic (D5a), hierarchy description (D6), R/C estimates (D8), book delay rules (D11) to derive updated timing targets therefrom (D8a); - a floor planning step (S9) based on updated book level logic (D5a), hierarchy description (D6), updated timing targets (D8a), and book physical models (D12) to evaluate the relative placement and shape of the bit-stacks and random clusters, to update timing targets (D8b), and to generate placement control oriented physical data (D13); - a placement step (S10) based on updated book level logic (D5a), and updated timing targets ( D8b), and placement control oriented physical data (D13) generated at previous step (S9) to achieve the placement of the partitions which are not already placed and generate wiring oriented physical data (D13a), and updated timing targets (D8c); - a wiring step (S11) based on updated book level logic (D5a), the sorted netlist (D7), wiring oriented physical data (D13a), updated timing targets (D8b) to ensure an optimal wiring of said partitions and generate updated timing targets (D8c) and physical data (D13a); - a timing validation step (S12) based on updated timing targets (D8c), updated book level logic (D5a), hierarchy description (D6) to make sure that real timings data (D8d) correspond to the initial timing targets R/C estimates; and, - a mask data generation step (S13) using said physical data (D13b) to produce mask data (D14) usable in the manufacturing of integrated circuit chips.

Claim 5

The method of any above claim characterized in that said logical macrofunctions are made from pre-qualified books.

Claim 6

The method of any above claim characterized in that all possible gaps between power busses and said macrofunctions are eliminated thanks to a dynamic allocation of said power busses.

Claim 7

The method of any above claim characterized in that said wiring step (S11) includes the wiring of the bit-stacks, made up of three passes, which are a control lines routing first, an intra-words routing second and an inter-words routing third, that provide an optimal wiring and can be fully automated.

Claim 8

The method of any above claim characterized in that it further includes the step of directly forming mask patterns onto said semiconductor integrated circuit chips by E. Beam lithography using said mask data (D14).