Patent EP0537973A2 successfully refreshed from Google Patents.
EP0537973A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Nand-cell type electrically erasable and programmable read- only memory with redundancy circuit
Assignee: Toshiba Corp
•
Filing: 1992-10-13
•
Granted: —
•
Expires: 2012-10-13
Abstract
Abstract A NAND-cell type electrically erasable and programmable read only memory (20) includes an array (21) of rows and columns of memory cells associated with parallel bit lines on a semiconductive substrate. Each memory cell essentially consists of a floating-gate field effect transistor having a floating gate and an insulated control gate. The memory cell array (21) is divided into a plurality of cell blocks, each of which includes NAND cell sections each including a predetermined number of a series-connected memory cell transistors. A redundancy cell section is provided which includes an array of redundancy memory cells containing at least one spare cell block. A row redundancy circuit (29) is connected to a row decoder (22), and is responsive to an address buffer (28). The redundancy circuit (30) replaces a defective block containing a defective memory cell or cells with the spare cell block.
Inventors
- 👤 Yoshiyuki c/o Intellectual Prop. Div. Tanaka
- 👤 Yasuo c/o Intellectual Prop. Div. Itoh
- 👤 Masaki c/o Intellectual Prop. Div. Momodomi
- 👤 Yoshihisa c/o Intellectual Prop. Div. Iwata
- 👤 Tomoharu c/o Intellectual Prop. Div. Tanaka
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-09 06:31
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/70; G11C29/78; G11C29/785; G11C29/789; G11C16/00; G11C16/02; G11C16/04; G11C16/0483; G11C29/80; G11C29/808; G11C29/816; G11C29/82
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
181 words
An electrically erasable and programmable non-volatile semiconductor memory device comprising a semi-conductive substrate (11), an array (21) of rows and columns of memory cells (M) on said substrate, each of said memory cells including a transistor (M) having a charge storage layer (14) insulatively arranged above said substrate and an insulated control gate electrode (16) overlying said charge storage layer and allowing charge carriers to move to or from said charge storage layer (14), said array (21) of memory cells being divided into a plurality of blocks, each of which includes a plurality of NAND cell sections each including a predetermined number of a series circuit of memory cell transistors (M1-M8), and a plurality of bit lines (BL) connected to said NAND cell sections, characterized in that said device further comprises a redundancy cell section (32) including an array of redundancy memory cells containing at least one spare cell block (32-1, 32-2), and redundancy circuit means (29) associated with said cell blocks, for replacing a defective block containing a defective memory cell or cells with the spare cell block (32-1, 32-2).
Claim 2
Dependent Claim
38 words
The memory device according to claim 1, characterized in that said spare cell block (32-1, 32-2) includes a plurality of NAND cell sections, each of which includes a predetermined number of a series circuit of memory cell transistors.
Claim 3
Dependent Claim
23 words
The memory device according to claim 2, characterized in that said redundancy cell section includes a plurality of spare cell blocks (32-1, 32-2).
Claim 4
Dependent Claim
70 words
The memory device according to claim 3, characterized in that said redundancy circuit means (29) comprises address storage circuit means (44) for holding an address of the defective block, logic circuit means (50) being responsive to said address storage circuit means, for determining a replacement of the defective block with the spare block, and signal generator circuit means (52) for providing said logic circuit means (50) with an activation signal.
Claim 5
Dependent Claim
53 words
The memory device according to claim 2, characterized by further comprising a first switching transistor (S1) arranged between one end of each NAND cell section and a corresponding bit line (BLi), and a second switching transistor (S2) coupled between an opposite end of each NAND cell section and a common source potential (Vs).
Claim 6
Dependent Claim
61 words
The memory device according to claim 2, characterized by further comprising redundancy column section (34) adjacent to the columns of said memory cell array (21) on said substrate (11) and including at least one spare column, and column redundancy circuit means (30) for replacing a defective column found in said columns of said memory cell array (21) with said spare column.
Claim 7
Dependent Claim
21 words
The memory device according to claim 6, characterized in that said redundancy column section (34) includes a plurality of spare columns.
Claim 8
Dependent Claim
75 words
The memory device according to claim 7, characterized in that said column redundancy circuit means (30) comprises column-address storage circuit means (64) for storing an address of the defective column, column replacement logic circuit means (66) being responsive to said column-address storage circuit means, for determining a replacement of the defective column with the spare column, and signal generation circuit means (68) for providing said column replacement logic circuit means (66) with an activation signal.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.