Architecture and method for combining static cache memory and dynamic main memory on the same chip (CDRAM)

Claim 2

The system of claim 1, further comprising: cache tag means (101, 201) for storing the identity of a plurality of lines of data "N" bits wide that exist in the second array; and comparator means (103, 203) for determining whether or not an eternal memory access request matches the identity any of said lines of data stored in the cache tag means (101, 201), the comparator (103, 203) having an output to signal a "hit" if a match is found and an output to signal a "miss" if no match is found.

Claim 3

The system of claim 2, further comprising: control means (104, 204) for activating the first transfer means to be followed by an activation of the second transfer means when the comparator means (103, 203) outputs a "miss".

Claim 4

The system of claim 3, wherein: the first and second transfer means interact with lines of memory cells in the first array that are not the same.

Claim 5

The system of claim 4, wherein: the first transfer means flushes a line of data previously identified in said cache tag means (101, 201); and the second transfer means fetches a line of data to be thereafter identified in said cache tag means (101, 201).

Claim 6

The system of claim 1, further comprising: data selection means (64, 65) for transferring less than "N" number of bits in response to an external memory access request.

Claim 7

The system of claim 1, wherein: first and second arrays and first and second transfer means are simultaneously disposed within a single semiconductor chip.

Claim 8

The system of claim 6, wherein: integer "P" is equal to one; and the data selection means selects one of "N" number of data line bits in the second array.

Claim 9

A cache memory system (60), comprising: a first array of DRAM memory cells (77) having a first access speed, the first array having dimensions "M" by "N" with each dimension being an integer number greater than one; a second array of SRAM memory cells (61) having a second access speed, said second access speed being substantially faster than said first access speed, the second array having dimensions "N" by "P", with dimension "P" being an integer number not less than one;    first transfer means to write "N" number or bits of data in parallel from the second array to the first array, the first transfer means flushes a line of data previously identified in said cache tag means; second transfer means to write "N" number of bits of data in parallel from the first array to the second array, the first and second transfer means interact with lines of memory cells in the first array that are not the same, the second transfer means fetches a line of data to be thereafter identified in said cache tag means (101); cache tag means (101) for storing the identity of a plurality of lines of data "N" bits wide that exist in the second array (61); comparator means (103) for determining whether or not an external memory access request matches the identity any of said lines of data stored in the cache tag means (101), the comparator (103) having an output to signal a "hit" if a match is found and an output to signal a "miss" if no match is found; control means (104) for activating the first transfer means to be followed by an activation of the second transfer means when the comparator means (103) outputs a "miss"; and data selection means (64, 65) for transferring less than "N" number of bits in the second array in response to an external memory access request.

Claim 10

The system of claim 9, wherein: integers "M" and "N" are both equal to a power of two.

Claim 11

A memory system (200) having a plurality of memory chips (120), each chip comprising: a first array of dynamic memory cells (150) with a first access speed, said first array having dimensions of "M" rows of bits by "N" columns of bits, said "M" and said "N" numbers being positive integers; a second array off static memory cells (122) having a second access speed that is substantially faster than said first access speed, the second array having dimensions of "P" rows of bits by "N" columns of bits, said "P" number being a positive integer less than said "M" number; and first transfer means for writing a line "K" bits long in parallel from the second array to the first array, said "K" being an integer and a fractional part of an addressed row of "N" bits; and second transfer means for writing a line "K" bits long in parallel from the first array to the second array.

Claim 12

The system of claim 11, further comprising: cache tag means (201) for storing a code responsive to the source addresses in the first array of a plurality of lines of data "K" bits wide that are duplicated in the second array; and comparator means (203) for determining whether or not an external memory access request matches said address code of any of said lines of data stored in the cache tag means (201), the comparator (203) having an output to signal a "hit" if a match is found and an output to signal a "miss" if no match is found.

Claim 13

The system of claim 12, further comprising: control means (204) for activating the first transfer means to be followed by an activation of the second transfer means when the comparator means outputs a "miss"

Claim 14

The system of claim 13, wherein: the first and second transfer means operate on lines of memory cells in the first array representing copies of different parts of the first array.

Claim 15

The system of claim 14, wherein: the first transfer means writes a line of data previously identified in said cache tag means (201) such that a representative part of the first array is updated; and the second transfer means copies a line of data represented in the first array to be thereafter identified by address code in said cache tag means (201).

Claim 16

The system of claim 11, further comprising: data selection means (130, 126, 134) for transferring at least one bit and less than "K" number of bits in response to an external memory access request.

Claim 17

The system of claim 11, wherein: first and second arrays and first and second transfer means are integrated within a single semiconductor chip.

Claim 18

The system of claim 16, wherein: integer "P" is equal to one; and the data selection means selects one of "K" number of data line bits in the second array.