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EP0535694A2
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EP
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Semiconductor memory device and method of manufacturing the same
Assignee: Toshiba Corp
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Filing: 1992-10-02
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Granted: —
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Expires: 2012-10-02
Abstract
Abstract When the surfaces of a selection gate electrode (4) and a floating gate electrode (5) are thermally oxidized with the selection gate electrode (4) disposed below the floating gate electrode (5), the thickness of a gate oxide film (81) formed on the selection gate electrode can be made larger than that of a gate oxide film (8) formed on the other portion. As a result, the coupling ratio of a memory transistor can be increased. Thus, the coupling ratio can be adequately increased by partly increasing the thickness of the insulation film between the floating gate electrode (5) and the semiconductor substrate (1). <IMAGE>
Inventors
- 👤 Hirohito C/O Intellectual Property Div. Taneda
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-09 04:05
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0411; H10D30/60; H10D30/68; H10D30/681; H10D30/683; H10D30/6891; H10D30/6892; H10D30/6894; H10D64/00; H10D64/01; H10D64/031; H10D64/035; H10B; H10B69/00
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
297 words
A semiconductor memory device comprising: a semiconductor substrate (1) of a first conductivity type; first and second impurity diffusion layers (31, 3) of a second conductivity type formed in said semiconductor substrate (1) with a preset distance from each other; a selection gate electrode (4) formed over that area of said semiconductor substrate (1) which lies between said first and second impurity diffusion layers (31, 3); a third impurity diffusion layer (32) of said second conductivity type formed in an area of said semiconductor substrate (1) which is different from the area lying between said first and second impurity diffusion layers (31, 3) and is set at a preset distance from said first impurity diffusion layer (31); a first gate oxide film (8, 81) formed on the area of said semiconductor substrate (1) lying between said first and second impurity diffusion layers (31, 3) and an area of said semiconductor substrate (1) lying between said first and third impurity diffusion layers (31 32), formed to be at least partly superposed on said selection gate electrode (4) and having a tunnel oxide film (7) formed on said first impurity diffusion layer (31); a floating gate electrode (5) formed on portions of said first gate oxide film (7, 8, 81) which lie over the area of said semiconductor substrate (1) lying between said first and second impurity diffusion layers (31, 3) and the area of said semiconductor substrate (1) lying between said second and third impurity diffusion layers (31, 32) and formed to be at least partly disposed over said selection gate electrode (4); a second gate oxide film (11) formed on said floating gate electrode (5); and a control gate electrode (6) formed over said floating gate electrode (5) with said second gate oxide film (11) disposed therebetween.
Claim 2
Dependent Claim
326 words
A semiconductor memory device comprising: a semiconductor substrate (1) of a first conductivity type; an element isolation region (12) formed on said semiconductor substrate (1) to divide said semiconductor substrate (1) into first and second element regions; first and second impurity diffusion layers (31, 3) of a second conductivity type formed at a preset distance from each other in said first element region; a selection gate electrode (4) formed over that area of said first element region which lies between said first and second impurity diffusion layers (31, 3); a third impurity diffusion layer (32) of said second conductivity type formed at a preset distance from said first impurity diffusion layer (31) and formed in an area of said first element region different from the area lying between said first and second impurity diffusion layers (31, 3); a first gate oxide film (8, 81) formed on the area of said first element region lying between said first and second impurity diffusion layers (31, 3) and the area of said first element region lying between said first and third impurity diffusion layers (31, 32), formed to be at lease partly superposed on said selection gate electrode (4) and having a tunnel oxide film (7) formed on said first impurity diffusion layer (31); a floating gate electrode (5) formed on portions of said first gate oxide film (7, 8, 81) which lie over the area of said first element region lying between said first and second impurity diffusion layers (31, 3) and the area of said first element region lying between said first and third impurity diffusion layers (31, 32) and formed to be at least partly disposed over said selection gate electrode (4); a second gate oxide film (82) formed on said second element region of said semiconductor substrate substrate (1); and a control gate electrode formed (6) on said second gate oxide film (82) and formed to be partly connected to said floating gate electrode (5).
Claim 3
Dependent Claim
35 words
A semiconductor memory device according to claim 1 or 2, characterized in that said semiconductor substrate (1) is formed of silicon single crystal and said selection gate electrode (4) is formed of polysilicon containing impurity.
Claim 4
Dependent Claim
45 words
A semiconductor memory device according to claim 1 or 2, characterized in that said selection gate electrode (4) is formed in a groove (2) which is formed in a portion of said semiconductor substrate lying between said first and second impurity diffusion layers (31, 3).
Claim 5
Dependent Claim
61 words
A semiconductor memory device according to claim 3, characterized in that the thickness of a portion (81) of said first gate oxide film (7, 8, 81) which is formed on said selection gate electrode (4) is larger than the thickness of a portion (8) of said first gate oxide film (7, 8, 81) which is formed on said semiconductor substrate (1).
Claim 6
Dependent Claim
25 words
A semiconductor memory device according to claim 1 or 2, characterized in that said second impurity diffusion layer (3) is formed with an LDD structure.
Claim 7
Independent Claim
272 words
A method of manufacturing a semiconductor memory device comprising the steps of: doping an impurity into a preset area of a semiconductor substrate (1) of a first conductivity type formed of silicon single crystal to form a channel portion; forming a selection gate electrode (4) over said preset area of said semiconductor substrate (1) with a gate oxide film (4a) disposed therebetween; forming a first impurity diffusion layer (31) of a second conductivity type in said semiconductor substrate (1) in contact with said selection gate electrode (4); forming a first gate oxide film (8, 81) which has a tunnel oxide film (7) formed on said first impurity diffusion layer (31) on the entire surface of said semiconductor substrate (1), said selecting gate electrode (4) and said first impurity diffusion layer (31) so as to be at least partly superposed on said selection gate electrode (4); forming a first conductive layer (5') for a floating gate electrode (5) on said first gate oxide film (7, 8, 81) so as to be at least partly disposed over said selection gate electrode (4); forming a second gate oxide film (11') on said first conductive layer (5') for the floating gate electrode (5); forming a second conductive layer (6') for a control gate electrode (6) on said second gate oxide film (11'); patterning said first gate oxide film (8, 81), said first conductive layer (5'), said second gate oxide film (11') and said second conductive layer (6') into a preset pattern; and forming second and third impurity diffusion layers (3, 32) in a preset area of said semiconductor substrate (1) in contact with said preset pattern.
Claim 8
Independent Claim
257 words
A method of manufacturing a semiconductor memory device comprising the steps of: forming an element isolation region (12) on a semiconductor substrate (1) of a first conductivity type formed of silicon single crystal to isolate said semiconductor substrate (1) into first and second element regions; forming a selection gate electrode (4) over said first element region with a gate oxide film (4a) disposed therebetween; forming first and second impurity diffusion layers (31, 3) of a second conductivity type in preset areas in contact with opposite side surfaces of said selection gate electrode (4), respectively; forming a third impurity diffusion layer (32) of said second conductivity type in said first element region of said semiconductor substrate (1) at a preset distance from said first impurity diffusion layer (31); forming a first gate oxide film (8, 81) which has a tunnel oxide (7) film formed on said first impurity diffusion layer (31) on the entire surface of said second impurity diffusion layer (3) on said first element region of said semiconductor substrate (1) so as to be at least partly superposed on said selection gate electrode (4), and at the same time, forming a second gate oxide film (82) on said second element region; and forming a floating gate electrode (11) on said first gate oxide film (8, 81) so as to be at least partly disposed over said selection gate electrode (4), and at the same time, forming a control gate electrode (6) in connection with said floating gate electrode (5) on said second gate oxide film (11).
Claim 9
Dependent Claim
60 words
A method of manufacturing a semiconductor memory device according to claim 7 or 8, further comprising the step of forming a groove (2) in a preset area on said semiconductor substrate (1) before the step of forming said selection gate electrode (4), and said selection gate electrode (4) is formed in said groove (2) through a gate insulating layer (4a).
Claim 10
Dependent Claim
26 words
A method of manufacturing a semiconductor memory device according to claim 7 or 8, characterized in that said selection gate electrode (4) is formed of polysilicon.
Claim 11
Dependent Claim
80 words
A method of manufacturing a semiconductor memory device according to claim 10, characterized in that said step of forming said first gate oxide film (7, 8, 81) includes a step of forming a thin gate oxide film (8) on said semiconductor substrate (1) and forming a thick gate oxide film (81) on said selection gate electrode (4) by utilizing a difference between the oxidation speed of said semiconductor substrate (1) and that of polysilicon of said selection gate electrode (4).
Claim 12
Dependent Claim
48 words
A method of manufacturing a semiconductor memory device according to claim 10, characterized in that said the thickness of said first gate oxide film (81) formed on said selection gate electrode (4) is adjusted by changing the impurity concentration of said selection gate electrode (4) formed of polysilicon.
References Cited (Backward Citations)
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