Patent EP0534007A1 successfully refreshed from Google Patents.
EP0534007A1
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EP
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Differential amplifier arrangement
Assignee: Nokia Bell NV
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Filing: 1991-09-25
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Granted: —
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Expires: 2011-09-25
Abstract
Abstract An operational transconductance amplifier (OTA) including a differential amplifier (M1/3) with a differential pair (M1/2) connected (VS) to a common current source (M3), and a control circuit (A, R1/2, M8/11) for obtaining a linear input volatge versus output current characteristic by maintaining the transconductance (gm) independent of the differential (VG2-VG1) and of the common mode (VG2+VG1) input voltages. The control circuit includes a negative feedback circuit with a comparator or operational amplifier (A) whose inputs are connected to the above connection point (VS) and to a reference terminal (Vref) whose voltage follows that of the differential inputs (VG1/2), the output of the comparator (A) controlling the current source (M3). The slope of the linear characteristic can also be modified by changing the voltage at the reference terminal (Vref) via an external input voltage terminal (VC). An additional current mirror circuit (M4/7), also controlled by the control circuit, is provided for suppressing the common mode output current in the differential pair (M1/2), this current being generated by the action of the control circuit on the current source (M3).
Inventors
- 👤 Joannes Mathilda Josephus Sevenhans
- 👤 Mark Gerrit Steven Jozef Van Paemel
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-09 05:29
CPC Classifications
H; H03; H03F; H03F3/00; H03F3/45; H03F3/45071; H03F3/45076; H03F3/45179; H03F1/00; H03F1/32; H03F1/3211; H03F3/45183; H03F3/45479; H03F3/45632; H03F3/45636; H03F3/45681; H03F3/4569; H03F3/45695; H03F3/4573; H03F3/45739; H03F2203/00; H03F2203/45; H03F2203/45008; H03F2203/45074; H03F2203/45078; H03F2203/45466; H03F2203/45612; H03F2203/45641; H03F2203/45648
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
121 words
Differential amplifier arrangement including a differential pair (M1, M2) comprising two individual amplifier branches with first (VG1) and second (VG2) input terminals and connected in a junction point (VS) to a common branch including a current source (M3), the current of said current source being regulated by a control circuit (A; R1, R2; M8, M9; M10, M11) so as to linearize an input/output characteristic of said differential pair, characterized in that said control circuit (A; R1, R2; M8, M9; M10, M11) includes a negative feedback circuit with a comparator (A) whose inputs are connected to a reference terminal (Vref) to which a reference voltage (Vref) is applied and to said junction point (VS), and whose output controls said current source (M3).
Claim 2
Dependent Claim
44 words
Differential amplifier arrangement according to claim 1, characterized in that said comparator (A) is an operational amplifier having a non-inverting (+) and an inverting (-) input, said junction point (VS) and said reference terminal (Vref) being connected to said non-inverting and inverting inputs respectively.
Claim 3
Dependent Claim
37 words
Differential amplifier arrangement according to claim 1, characterized in that said reference terminal (Vref) is so coupled to said input terminals (VG1, VG2) that said reference voltage (Vref) follows the common mode voltage on said input terminals.
Claim 4
Dependent Claim
75 words
Differential amplifier arrangement according to claim 3, characterized in that said control circuit (A; R1, R2; M8, M9; M10, M11) further includes a first (M8) and a second (M9) interface means and a voltage divider (R1, R2), and that said reference terminal (Vref) is a tapping point of said voltage divider whose input terminals (VX, VY) are coupled through said first and second interface means to said first and second input terminals (VG1, VG2) respectively.
Claim 5
Dependent Claim
47 words
Differential amplifier arrangement according to claim 3, characterized in that said control circuit (A; R1, R2; M8, M9; M10, M11) further includes means (M8, M9; M10, M11; R1, R2) to derive said reference voltage (Vref) as a sum of said common mode voltage and a predetermined voltage.
Claim 6
Dependent Claim
101 words
Differential amplifier arrangement according to claims 4 and 5, characterized in that said first (M8) and second (M9) interface means are respectively connected in series with a second (M10) and third (M11) current sources, said output terminals (VX, VY) of said voltage divider (R1; R2) being connected to the junction points of said first interface means (M8) and said second current source (M10) and of said second interface means (M9) and said third current source (M11), respectively, the current in said second and third current sources being regulated via a control input terminal (VC) through which said predetermined voltage is adjusted.
Claim 7
Dependent Claim
53 words
Differential amplifier arrangement according to claim 1, characterized in that it further includes current mirror circuitry (M7, M6; M4, M5) controlled by said control circuit (A; R1, R2; M8, M9; M10, M11) and of which the outputs are coupled to said individual amplifier branches (M1, M2) for suppressing common mode output currents therein.
Claim 8
Dependent Claim
59 words
Differential amplifier arrangement according to claim 7, characterized in that said current mirror circuitry (M7, M6; M4, M5) includes a fourth current source (M7) connected in series with a current mirror (M6) and a fifth M4 and a sixth (M5) current sources connected in series with distinct ones of said individual amplifier branches and controlled by said current mirror.
Claim 9
Dependent Claim
36 words
Differential amplifier arrangement according to any of the previous claims, characterized in that said individual amplifier branches (M1, M2) and said current sources (M3, M10, M11, M7, M4. M5) each include at least one MOS transistor.
Claim 10
Dependent Claim
24 words
Differential amplifier arrangement according to claim 4 or 6, characterized in that said interface means (M8, M9) each include at least one MOS transistor.
Claim 11
Dependent Claim
40 words
Differential amplifier arrangement according to claim 4 or 6, characterized in that said voltage divider comprises a first (R1) and a second (R2) substantially equal resistors connected in series, the junction point of said resistors constituting said tapping point (Vref).
Claim 12
Dependent Claim
20 words
Differential amplifier arrangement according to any of the previous claims, characterized in that it is integrated in an electronic chip.
References Cited (Backward Citations)
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