Data processing system with address translation function for different page sizes

Abstract

Abstract The data processing system translates a logical address made up of a partial space number, a logical space number and an address within a page to a physical address made up of a physical page number and the address within a page and accesses a memory section under the coexistence of a plurality of page sizes. The system further comprises a table holding section for holding a plurality of sets of copies of a plurality of address translation tables stored in the memory section on a partial space basis. The plurality of sets of copies are each assigned to a particular page size. A load control section loads one of the plurality of address translation tables into the table holding section in response to an address translation table load command. A directory supervising section supervises partial spaces each corresponding to one of the plurality of address translation tables held in the table holding section. A first loading section executes by defining the partial spaces assigned to the same page size as a single supervisory unit in the directory supervising section, load control over the plurality of address translation tables independently. This data processing system is capable of translating addresses having a plurality of page sizes dynamically to thereby enhance efficient use of a memory and improve the overhead of an operating system.

Inventors

• 👤 Yoshifumi c/o NEC Corporation Fujiwara
• 👤 Hiroshi c/o NEC Koufu Ltd. Kato

Bibliographic Details