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EP0532295A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

Gray scale correction circuit

Assignee: Panasonic Holdings Corp
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Filing: 1992-09-09
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Granted: —
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Expires: 2012-09-09
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Abstract

Abstract This invention relates to a gray level correction circuit for effective use of the cathode ray tube with a small dynamic range, and has as its object to make a gray level correction on the video signal which has passed the contrast circuit and on the video signal with any value of contrast without making the picture whitish. A gray level correction circuit comprising: a cumulative histogram circuit (1) for forming a cumulative histogram for each field of the input video signal, and outputting a result; a first multiplier circuit (2) for multiplying output of the cumulative histogram circuit (1) by a first constant; a normalizing circuit (3) for normalizing output of the first multiplier circuit (2) by diving by the total number of samples, and outputting a normalized signal; an interpolation circuit (4) for outputting a correction value for each pixel by using output of the normalizing circuit (3) and the input video signal; a second multiplier circuit (5) for multiplying output of the interpolation circuit (4) by a second constant; and an adder circuit (6) for adding output of the second multiplier circuit (5) to the input video signal.

Inventors

  • 👤 Naoji Okumara
  • 👤 Yosuke Izawa

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-11-09 14:14
CPC Classifications
G; G06; G06T; G06T5/00; G06T5/90; G06T5/92; G06T5/40; H; H04; H04N; H04N5/00; H04N5/14; H04N5/20

Claims Analysis

Total Claims: 1
Claim 1
Independent Claim 127 words
A gray level correction circuit comprising: a cumulative histogram (1) for forming a cumulative histogram for each field of the input video signal; a first multiplier circuit (2) for multiplying output of said cumulative histogram circuit (1) by a first constant; a normalizing circuit (3) for normalizing output of the first multiplier circuit (2) by dividing by the total number of samples, and outputting a normalized signal; an interpolation circuit (4) for outputting a correction value for each pixel by using output of said normalizing circuit and the input video signal; a second multiplier circuit (5) for multiplying output of said interpolation circuit (4) by a second constant; and an adder circuit (6) for adding output of the second adder circuit (5) to the input video signal.

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