Patent EP0530159A2 successfully refreshed from Google Patents.
EP0530159A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Zero-consumption power-on reset circuit
Assignee: STMicroelectronics SRL
•
Filing: 1992-08-27
•
Granted: —
•
Expires: 2012-08-27
Abstract
Abstract A power-on reset circuit utilizes capacitive couplings and does not establish any static current path bewteen the supply rails. The circuit has a null static consumption and may be advantageously integrated in CMOS micrologics. Moreover the circuit is insensitive to rebounds on the supply rails and to internal and external noise.
Inventors
- 👤 Luigi Pascucci
- 👤 Marco Olivo
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-08 16:21
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/22; H03K17/223; H03K2217/00; H03K2217/0036
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
183 words
A power-on reset circuit having a null static consumption, capable of generating through an output a resetting signal which upon powering the integrated circuit follows the rise of the supply voltage up to the design value and thereafter stably switches to ground potential, characterized by comprising cascade-connected first and second inverters, the output of the second inverter constituting the output of the power-on reset circuit, the connection node between the two inverters being capacitively coupled to ground and the input of the first inverter being capacitively coupled to the supply rail; a first switch driven by the signal present on said connection node between the inverters, functionally connected between said input node of the first inverter and the supply rail; a second switch functionally connected between said input node of the first inverter and ground and having a control terminal; a biasing line connected to the supply rail and capacitively coupled to ground which comprises at least two series-connected forward biased junctions, the node of capacitive coupling to ground of the line being functionally connected to said control terminal of said second switch.
Claim 2
Dependent Claim
38 words
A circuit as defined in claim 1, wherein said two forward biased junctions in series are constituted by two diodes functionally connected in series, the connection node between the two diodes in series being capacitively coupled to ground.
Claim 3
Dependent Claim
33 words
A circuit as defined in claim 1, wherein a third switch driven by the supply voltage is functionally connected between said node of capacitive coupling to ground of said biasing line and ground.
Claim 4
Dependent Claim
109 words
A circuit as defined in claim 1, wherein a fourth switch is connected between a connection node between said two forward biased junctions and said control terminal of said second switch and is driven by the signal present on the connection node between said inverters, thus implementing upon the triggering of said first inverter, a feedback action capable of enhancing the discharge of the voltage present on the input node of the first inverter toward ground potential through said second switch and thus raising the potential on the control terminal of said second switch toward the potential of said connection node between said two junctions of the biasing line.
Claim 5
Dependent Claim
65 words
A circuit as defined in claim 1, wherein said integrated circuit has a P-type substrate connected to ground and said capacitive couplings to ground are established by means of integrated capacitors of an N-diffusion/P-substrate type and said capacitive coupling with the supply rail is realized by means of an integrated capacitor of a P-diffusion/N-well type wherein said N-well region is connected to the supply rail.
Claim 6
Dependent Claim
42 words
A circuit as defined in claim 5, wherein said second switch is an N-channel MOS transistor, said junctions connected in series of said biasing line are constituted by two diode-connected N-channel MOS transistors and said first switch is a P-channel MOS transistor.
Claim 7
Dependent Claim
46 words
A circuit as defined in claim 3, wherein said discharge switch which is controlled by the supply voltage is a P-channel MOS transistor capable of conducting when the supply voltage drops below the potential of said node of capacitive coupling to ground of said biasing line.
Claim 8
Dependent Claim
16 words
A circuit as defined in claim 4, wherein said fourth switch is an N-channel MOS transistor.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.