Patent EP0529330A2 successfully refreshed from Google Patents.
EP0529330A2
Expired / Lapsed
EP
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System with laser link decoder for DRAM redundancy scheme
Assignee: Texas Instruments Inc
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Filing: 1992-07-28
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Granted: —
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Expires: 2012-07-28
Abstract
Abstract A decoder for a memory redundancy scheme is disclosed which allows replacement of a number of memory cell locations in connection with the state of a plurality of fuses.
Inventors
- 👤 Hiep V. Tran
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-02 08:09
CPC Classifications
G; G11; G11C; G11C16/00; G11C29/00; G11C29/70; G11C29/78; G11C29/785; G11C29/787; G11C29/80; G11C29/808
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
69 words
A decoder comprising: a plurality of transistors; a signal line common to and connected to each of said plurality of transistors; a plurality of input circuits, each input circuit being connected to an associated one of said plurality of transistors and including a fuse; a plurality of fuses, being serially connected together, each fuse from said plurality being further connected to an associated one of said plurality of transistors.
Claim 2
Dependent Claim
15 words
A decoder as recited in claim 1 wherein each of said fuses are laser blowable.
Claim 3
Dependent Claim
18 words
A decoder as recited in claim 1 which further comprises precharge circuitry for connection to said signal line.
Claim 4
Dependent Claim
61 words
A decoder as recited in claim 1 wherein each said input circuit has first, second and third transistors, said first transistor being connected to the output of said inverter and said input circuit fuse, said second transistor being connected to the input of said inverter and said input circuit fuse, said third transistor being connected to said first and second transistors.
Claim 5
Dependent Claim
64 words
A decoder as recited in claim 1 which further includes: circuitry for disabling said decoder, said circuitry comprising a pair of transistors, each being operative to receive the complement of an input signal to the other from the pair; and a pair of fuses connected to said signal line, each said fuse from said pair being connected to an associated transistor from said pair.
Claim 6
Dependent Claim
14 words
A decoder as recited in claim 1, wherein each transistor is an n-channel transistor.
Claim 7
Dependent Claim
14 words
A decoder as recited in claim 1, wherein each transistor is a p-channel transistor.
Claim 8
Dependent Claim
14 words
A decoder as recited in claim 1, wherein each transistor is a bipolar transistor.
Claim 9
Dependent Claim
53 words
A decoder as recited in claim 4, wherein said first transistor is connected at its base to the output of said inverter and said third transistor and wherein said first transistor is connected at its drain to said input circuit fuse, the gate of said second transistor and the input of said inverter.
Claim 10
Dependent Claim
14 words
A dynamic random access memory including a decoder as claimed in any preceding claim.
Claim 11
Dependent Claim
15 words
An electronic system including a decoder as claimed in any of claims 1 to 9.
Claim 12
Dependent Claim
14 words
An electronic system including a dynamic random access memory as claimed in claim 10.
Claim 13
Dependent Claim
37 words
An electronic system as claimed in claim 11 or claim 12 wherein said system is selected from the group consisting of printers, copiers, electronic storage devices (memories), high definition television, enhanced definition television, telecommunications and computational devices.
References Cited (Backward Citations)
No citation records indexed.
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