Patent EP0528283A2 successfully refreshed from Google Patents.
← Back to Patent Explorer
EP0528283A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

Semiconductor integrated circuit having clock signal generator

Assignee: Sony Corp
•
Filing: 1992-08-06
•
Granted: —
•
Expires: 2012-08-06
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A semiconductor integrated circuit having a clock signal generator comprising a ring oscillator (20), a divider (14), a phase comparator (15), and an up-down counter (16). The ring oscillator (20) provides variable oscillation frequencies determined by a sum of the delay times provided by the circuit elements constituting the oscillator. The divider (14) divides the oscillation frequency from the ring oscillator (20) by a specified number. The phase comparator (15) compares the frequency of the signal from the divider (14) with the frequency of the external clock signal (S fe ). The up-down counter (16) controls the oscillation frequency of the ring oscillator (20) based on the comparison result from the comparator (15). The clock generator is controlled by an external clock signal (S fe ) to generate an Internal clock signal (S fc ) having a higher frequency and outputs both signals. By use of a digital integrated circuit technology alone, it becomes possible to include slow operating semiconductor elments and fast operating semiconductor elements on the same circuit chip without sacrificing the excellent characteristics of the latter.

Inventors

  • 👤 Takano Chiaki

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-11-08 15:03
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/099; H03L7/0995; H03L7/0997; G; G06; G06F; G06F1/00; G06F1/04; G06F1/08; H03K; H03K3/00; H03K3/02; H03K3/027; H03K3/03; H03K3/0315; H03L7/085; H03L7/089; H03L7/16; H03L7/18; H03L7/183

Claims Analysis

Total Claims: 4
Claim 1
Independent Claim 99 words
A semiconductor integrated circuit having a clock signal generator comprising: a ring oscillator for providing variable oscillating frequencies determined by a sum of the delay times provided by the circuit elements constituting said oscillator; a divider for dividing the oscillation frequency given from said ring oscillator by a specified number; a phase comparator for comparing the frequency of the output signal given from said divider with the frequency of the external clock signal given from the outside; and an up-down counter for controlling the oscillation frequency of said ring oscillator based on the comparison result from said phase comparator.
Claim 2
Dependent Claim 27 words
A semiconductor integrated circuit having a clock signal generator according to Claim 1, wherein said semiconductor integrated circuit is composed of both compound semiconductors and Si semiconductors.
Claim 3
Dependent Claim 138 words
A semiconductor integrated circuit having a clock signal generator comprising: a ring oscillator for providing variable oscillating frequencies determined by a sum of the delay times provided by the circuit elements constituting said oscillator; a divider for dividing the oscillation frequency given from said ring oscillator by a specified number; a phase comparator for comparing the frequency of the output signal given from said divider with the frequency of the external clock signal given from the outside; and an up-down counter for controlling the oscillation frequency of said ring oscillator based on the comparison result from said phase comparator; wherein said clock signal generator, controlled by said externally entered clock signal to generate an internal clock signal of which frequency is higher than the frequency of said externally entered clock signal, outputs both internal and external clock signals.
Claim 4
Dependent Claim 138 words
A semiconductor integrated circuit having a clock signal generator comprising: a ring oscillator for providing variable oscillating frequencies determined by a sum of the delay times provided by the circuit elements constituting said oscillator; a divider for dividing the oscillation frequency given from said ring oscillator by a specified number; a phase comparator for comparing the frequency of the output signal given from said divider with the frequency of the external clock signal given from the outside; and an up-down counter for controlling the oscillation frequency of said ring oscillator based on the comparison result from said phase comparator; wherein said clock signal generator generates an internal clock signal of which frequency is higher than the frequency of said externally entered clock signal to operate the circuit elements internal to said clock signal generator at a high speed.

References Cited (Backward Citations)

No citation records indexed.

USPTO Annuity & Maintenance Windows

Maintenance schedule is calculated for granted US utility patents.

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag