Patent EP0528273A2 successfully refreshed from Google Patents.
EP0528273A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Buffer memory and method of managing the same
Assignee: Fujitsu Ltd
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Filing: 1992-08-05
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Granted: —
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Expires: 2012-08-05
Abstract
Abstract A buffer memory (14) having addressable locations into which data blocks received from one of two or more devices (10, 12) are written and from which those data blocks are read to one of the other devices, is managed by a buffer memory controller (16). Selected, not necessarily sequential, buffer addresses are assigned by the controller to store data blocks included in a series supplied from the first device, and these assigned buffer addresses are loaded into register locations of a list register (22). Buffer addresses are read from an ordered list of those register locations and respective data blocks are written into such addresses. Register locations from that list are accessed to retrieve buffer addresses therefrom, and the data blocks stored in the retrieved buffer addresses are read from the buffer memory to the second device. <IMAGE>
Inventors
- 👤 Manoj K. Samanta
- 👤 Timothy R. Feldman
- 👤 Clifford S. Fernalld, Jr.
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-06 17:40
CPC Classifications
G; G06; G06F; G06F3/00; G06F3/06; G06F3/0601; G06F13/00; G06F13/10; G06F13/12; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0862; G06F3/0628; G06F3/0655; G06F3/0656
Claims Analysis
Total Claims: 25
Claim 1
Independent Claim
152 words
A method of managing a buffer memory to communicate with first and second data devices, said buffer memory having addressable locations into which data blocks are written and from which data blocks are read, comprising the steps of: writing a series of data blocks from said first device into available, not necessarily sequential, locations of said buffer memory; creating in a list register having register locations an ordered address list of those buffer addresses into which the latest series of data blocks is written; indicating the register location in which is stored the buffer address of the first data block in said series to be read from said buffer memory to said second device; and progressively indicating the register locations in said ordered address list which contain the buffer addresses which store additional data blocks in said series to read said additional data blocks from said buffer memory to said second device.
Claim 2
Dependent Claim
76 words
The method of Claim 1 wherein the step of writing a series of data blocks into said buffer memory comprises providing a write pointer to identify a register location in said list register, reading the buffer address stored in the register location identified by the write pointer, writing a data block into the buffer address read from the register location identified by the write pointer, and advancing said write pointer to identify a next register location.
Claim 3
Dependent Claim
43 words
The method of Claim 1 or 2 wherein said step of creating an ordered address list comprises loading into a selected number of register locations of said list register respective buffer addresses into which the series of data blocks is to be written.
Claim 4
Dependent Claim
45 words
The method of Claim 3 wherein buffer addresses previously stored in at least some of said selected number of register locations are overwritten when the respective buffer addresses into which the series of data blocks is to be written are loaded into said list register.
Claim 5
Dependent Claim
34 words
The method of Claim 1, 2, 3 or 4 wherein said step of creating an ordered list further comprises pre-assigning selected buffer addresses for storing the series of data blocks to be written therein.
Claim 6
Independent Claim
127 words
A method of managing a buffer memory to transfer data between first and second devices, said buffer memory having addressable locations into which data blocks are written and from which data blocks are read, said method comprising the steps of: assigning selected not necessarily sequential buffer addresses to store data blocks included in a series of data blocks supplied from said first device; loading into selected register locations of a list register the assigned buffer addresses; reading buffer addresses from an ordered list of register locations and writing a respective data block into a buffer address read from a register location; and accessing progressive register locations to retrieve buffer addresses loaded therein for transferring to said second device the data blocks stored in the retrieved buffer addresses.
Claim 7
Dependent Claim
32 words
The method of Claim 6 wherein said ordered list of register locations into which the assigned buffer addresses are loaded differs from said progressive register locations from which buffer addresses are retrieved.
Claim 8
Dependent Claim
72 words
The method of Claim 6 or 7 wherein the step of reading buffer addresses from said ordered list of register locations comprises initially pointing to the register location in which is loaded the buffer address assigned to the first data block in said series, and pointing to a next register location when a data block from said first device is written into the buffer address read from the previously pointed-to register locations.
Claim 9
Dependent Claim
52 words
The method of Claim 8 wherein the step of pointing to a next register location continues from location to location in response to the writing of a data block into a respective buffer address until all of the data blocks in said series have been written into their respectively assigned buffer addresses.
Claim 10
Dependent Claim
36 words
The method of Claim 6, 7, 8 or 9 wherein said step of loading the assigned buffer addresses into selected register locations includes overwriting buffer addresses that may have been loaded previously into said register locations.
Claim 11
Independent Claim
75 words
The method of any of claims 6 to 10 wherein the step of accessing progressive register locations to retrieve buffer addresses comprises initially identifying the register location in which is loaded the buffer address assigned to the first data block in a series supplied from said first device, and identifying a next register location when a data block is transferred to the second device from the buffer address retrieved from the previously identified register location.
Claim 12
Dependent Claim
46 words
The method of Claim 11 wherein the step of identifying a next successive register location continues from location to location in response to the transferring of a data block from a respective buffer address until all of the data blocks in said series have been transferred.
Claim 13
Independent Claim
59 words
The method of any of claims 6 to 12 wherein said step of assigning selected buffer addresses to store data blocks includes assigning a buffer address that may presently store a data block, such that the presently stored data block is overwritten by a new data block included in the series of data blocks supplied from said first device.
Claim 14
Dependent Claim
144 words
Apparatus for transferring data from a first device to a second device, wherein a buffer memory having addressable locations stores data blocks received from said first device in addresses selected by a controller, said apparatus comprising: list register means having plural register locations for storing buffer addresses written thereinto by said buffer controller; first pointer means for reading out the buffer addresses written into selected locations of said list register means to create an ordered list of buffer addresses; buffer write means for writing a data block from said first device into the buffer address read from said list register means; second pointer means for accessing progressive locations of said list register means to retrieve therefrom the ordered list of buffer addresses; and transfer means for transferring to said second device the data blocks stored in the buffer memory at the retrieved buffer addresses.
Claim 15
Dependent Claim
50 words
The apparatus of Claim 14 wherein the number of register locations of the list register means from which buffer addresses are read by said first pointer means differs from the number of register locations of the list register means from which buffer addresses are retrieved by said second pointer means.
Claim 16
Dependent Claim
79 words
The apparatus of Claim 14 or 15 wherein the data blocks written into the buffer memory are called for by said second device and are included in a series of data blocks, and wherein said controller is operable to set said first pointer means to the register location of said list register means in which is stored the buffer address selected by said controller to store the first data block in the series called for by said second device.
Claim 17
Dependent Claim
48 words
The apparatus of Claim 14, 15, or 16 further comprising means for advancing said first pointer means to a next register location of said list register means in said ordered list when a data block is written into the buffer address last read from said list register means.
Claim 18
Dependent Claim
55 words
The apparatus of Claim 14, 15, 16, or 17 wherein said controller is operable to set said second pointer means to the register location of said list register means in which is stored the buffer address selected by said controller to store the first data block in the series called for by said second device.
Claim 19
Independent Claim
53 words
The apparatus of any of claims 14 to 18 further comprising means for advancing said second pointer means to a next register location of said list register means in said ordered list when a data block is transferred to said second device from the buffer address last retrieved from said list register means.
Claim 20
Dependent Claim
89 words
The apparatus of Claim 19 wherein said controller is operable to prefetch data blocks not called for by said second device, said prefetched data blocks and the data blocks called for by said second device being written into buffer addresses selected by said controller and stored in said list register means; and wherein said means for advancing said second pointer means includes means for stopping said second pointer means after the last data block in a series called for by said second device is transferred to said second device.
Claim 21
Independent Claim
104 words
The apparatus of any of claims 14 to 20 wherein the progressive register locations of said list register means from which the buffer addresses are retrieved differ from the selected register locations of said list register means from which the buffer addresses are read, and wherein said controller is operable to select a sequence of register locations and to write into the register locations of said selected sequence designated buffer addresses which subsequently are retrieved from said selected sequence of register locations by said second pointer means to transfer to said second device those data blocks which are stored in the retrieved buffer addresses.
Claim 22
Independent Claim
31 words
The apparatus of any of claims 14 to 21 wherein said controller is operable to designate those buffer addresses in which are stored data blocks called for by said second device.
Claim 23
Independent Claim
34 words
The apparatus of any of claims 14 to 22 wherein said controller is operable to overwrite buffer addresses previously written into at least some of said selected register locations with newly selected buffer addresses.
Claim 24
Dependent Claim
65 words
The apparatus of Claim 23 wherein said controller is operable to select buffer addresses to be written into said list register means and to have data blocks written thereinto by said buffer write means, which selected buffer addresses already store data blocks that had been previously written thereinto, whereby the previously stored data blocks are overwritten by new data blocks received from said first device.
Claim 25
Dependent Claim
128 words
The apparatus of Claim 16 wherein the data blocks written into the buffer memory are called for by said second device and are included in a series of plural data blocks, wherein said controller is operable to set both said first pointer means and said second pointer means to the register location of said list register means in which is stored the buffer address selected by said controller to store the first data block in the series called for by said second device, and further including means for advancing said first pointer means to a number of register locations in said ordered list corresponding to the number of data blocks included in said series and means for advancing said second pointer means to access the same register locations.
References Cited (Backward Citations)
No citation records indexed.
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