Semiconductor module
Abstract
Abstract To prevent a semiconductor device from breaking down due to a surge voltage which is generated by the existence of floating inductance in a terminal conductor drawn out from the connection of two semiconductor elements contained in one semiconductor container and which is applied to one of the elements when they are turned off, the invention provides a semiconductor device in which two pairs of a first and a second pair of electrode conductors each consists of a pair of a first electrode conductor onto which semiconductor elements with main electrodes are fixed on its bottom surface and a second electrode conductor connected to the main electrodes on the upper surface on the semiconductor elements by connecting leads are fixed on the bottom plate of a container via insulating plates, one main terminal conductor connected to the first electrode conductor of the first pair and another main terminal conductor connected to the second electrode conductor of the second pair are both drawn out externally, and one intermediate terminal conductor is connected to both the second electrode conductor of the first pair and the first electrode conductor of the second pair and drawn out externally wherein connecting conductor with a lower floating inductance and a higher resistance than in the part of the intermediate terminal conductor between the second electrode conductor of the first pair and the first electrode conductor of the second pair is connected across both electrode conductors in parallel to the intermediate terminal conductor. When semiconductor elements are connected to the respective semiconductor elements in parallel, the connecting conductors are installed at locations close to each semiconductor element of the electrode conductors.
Inventors
- 👤 Shinichi c/o Fuji Electric Co. Ltd. Kobayashi
- 👤 Tadashi C/O Fuji Electric Co. Ltd. Miyasaka
- 👤 Toshihisa c/o Fuji Electric Co. Ltd. Shimizu
Bibliographic Details
Claims Analysis
Total Claims: 4References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.