Improved thermal inkjet printhead structure and method for making the same

Claim 1

A thermal inkjet printhead apparatus having at least one MOSFET drive transistor (126) integrated thereon comprising: a substrate (70) comprised of silicon; a MOSFET transistor (126) positioned on said substrate (70), said transistor (70) comprising a source region (118), a drain region (120), and a gate (110) positioned between said source region (118) and said drain region (120), said gate (110) comprising: a layer (72) of silicon dioxide on said substrate (70); a layer of silicon nitride (76) on said layer (72) of silicon dioxide; and a layer (90) of polycrystalline silicon on said layer (76) of silicon nitride; a field oxide layer (84, 86) on said substrate (70), said field oxide layer (84, 86) surrounding said transistor (126) and being comprised of silicon dioxide; a layer (124) of dielectric material covering said field oxide layer (84, 86) and said transistor (126), said layer (124) of dielectric material having a plurality of openings (174, 176, 177) therethrough, said openings (174, 176, 177) providing access to said source region (118), said drain region (120), and said gate (110) of said transistor (126); a layer (180) of electrically resistive material positioned on said layer (124) of dielectric material, said layer of electrically resistive material (180) being in direct electrical contact with said source region (118), said drain region (120), and said gate (110) through said openings (174, 176, 177); a layer (181) of conductive material affixed to a portion of said layer (180) of electrically resistive material in order to form a multi-layer structure (182), said layer (180) of electrically resistive material in said multi-layer structure (182) having at least one uncovered section (202) wherein said layer (181) of conductive material is absent therefrom, said uncovered section (202) functioning as a heating resistor (209), said layer (180) of electrically resistive material being covered with said layer (181) of conductive material at said source region (118), said drain region (120), and said gate (110) of said transistor (126); a portion (220) of protective material positioned on said heating resistor (209); and a plate member (240) having at least one opening (242) therethrough, said plate member (240) being secured to said portion (220) of protective material, said portion (220) of protective material having a section thereof removed directly beneath said opening (242) through said plate member (240) in order to form an ink receiving cavity (250) thereunder, said heating resistor (209) being positioned beneath and in alignment with said ink receiving cavity (250) in order to impart heat thereto.

Claim 5

A method for manufacturing a thermal inkjet printhead apparatus having at least one MOSFET drive transistor (126) integrated thereon comprising the steps of: providing a substrate (70) comprised of silicon; forming a layer (72) of silicon dioxide on said substrate (70); forming a layer (76) of silicon nitride on said layer (72) of silicon nitride; removing a portion of said layer (76) of silicon nitride so as to leave a section (79) of silicon nitride remaining intact on said layer (72) of silicon dioxide, said section (79) of silicon nitride being surrounded by a plurality of exposed regions (80, 82) of said layer (72) of silicon dioxide; oxidizing said substrate (70) beneath said exposed regions (80, 82) of said layer (72) of silicon dioxide in order to form a field oxide layer (84, 86) surrounding said section (79) of silicon nitride; forming a layer (90) of polycrystalline silicon on said section (79) of silicon nitride, said layer (90) of polycrystalline silicon, said section (79) of silicon nitride, and said layer (72) of silicon dioxide thereunder together forming a gate (110) of said transistor (126); forming a transistor source region (118) and a transistor drain region (120) within said substrate (70) adjacent said gate (110); applying a layer (124) of dielectric material onto said field oxide layer (84, 86), said gate (110), said source region (118), and said drain region (120); forming a plurality of openings (174, 176, 177) through said layer (124) of dielectric material in order to provide access to said gate (110), said source region (118), and said drain region (120); applying a layer (180) of electrically resistive material onto said layer (124) of dielectric material, said layer (180) of electrically resistive material being in direct electrical contact with said gate (110), said source region (118), and said drain region (120) through said openings (174, 176, 177); applying a layer (181) of conductive material onto said layer (180) of electrically resistive material in order to form a multi-layer structure (182), said layer (181) of electrically resistive material in said multi-layer structure (182) having at least one uncovered section (202) wherein said layer (181) of conductive material is absent therefrom, said uncovered section (202) functioning as a heating resistor (209), said layer (180) of electrically resistive material being covered with said layer (181) of conductive material at said source region (118), said drain region (120), and said gate (110) of said transistor (126); applying a portion (220) of protective material onto said resistor (209); and securing a plate member (240) having at least one opening (242) therethrough onto said portion (220) of protective material, said portion (220) of protective material having a section thereof removed directly beneath said opening (242) through said plate member (240) in order to form an ink receiving cavity (250) thereunder, said heating resistor (209) being positioned beneath and in alignment with said ink receiving cavity (250) in order to impart heat thereto.

Claim 6

A method for manufacturing a thermal inkjet printhead apparatus having at least one MOSFET drive transistor (126) integrated thereon comprising the steps of: providing a substrate (70) comprised of silicon; forming a layer (72) of silicon dioxide on said substrate (70); forming a layer (76) of silicon nitride on said layer (72) of silicon nitride; removing a portion of said layer (76) of silicon nitride so as to leave a section (79) of silicon nitride remaining intact on said layer (72) of silicon dioxide, said section (79) of silicon nitride being surrounded by a plurality of exposed regions (80, 82) of said layer (72) of silicon dioxide; oxidizing said substrate (70) beneath said exposed regions (80, 82) of said layer (72) of silicon dioxide in order to form a field oxide layer (84, 86) surrounding said section (79) of silicon nitride; forming a layer (90) of polycrystalline silicon on said section (79) of silicon nitride, said layer (90) of polycrystalline silicon comprising an upper surface (96) and a lower surface (94), said lower surface (94) being adjacent said section (79) of silicon nitride, said forming of said layer (90) of polycrystalline silicon further comprising the step of etching said polycrystalline silicon so that said layer (90) of polycrystalline silicon continuously decreases in width from said lower surface (94) to said upper surface (96) thereof, said layer (90) of polycrystalline silicon, said section (79) of silicon nitride, and said layer (72) of silicon dioxide thereunder together forming a gate (110) in said transistor (126); forming a transistor source region (118) and a transistor drain region (120) within said substrate (70) adjacent said gate (110); applying a layer (124) of dielectric material onto said field oxide layer (84, 86), said gate (110), said source region (118), and said drain region (120); forming a plurality of openings (174, 176, 177) through said layer (124) of dielectric material in order to provide access to said gate (110), said source region (118), and said drain region (120); applying a layer (180) of electrically resistive material onto said layer (124) of dielectric material, said layer (180) of electrically resistive material being in direct electrical contact with said gate (110), said source region (118), and said drain region (120) through said openings (174, 176, 177), said layer (180) of electrically resistive material being comprised of a composition selected from the group consisting of polycrystalline silicon, and a mixture of tantalum and aluminum; applying a layer (181) of conductive material onto said layer (180) of electrically resistive material in order to form a multi-layer structure (182), said layer (180) of electrically resistive material in said multi-layer structure (182) having at least one uncovered section (202) wherein said layer (181) of conductive material is absent therefrom, said uncovered section (202) functioning as a heating resistor (209), said layer (180) of electrically resistive material being covered with said layer (181) of conductive material at said source region (118), said drain region (120), and said gate (110) of said transistor (126), said layer (181) of conductive material being comprised of a composition selected from the group consisting of aluminum, copper, and gold; applying a first passivation layer (222) comprised of silicon nitride onto said resistor (209); applying a second passivation layer (223) comprised of silicon carbide onto said first passivation layer (222); applying a cavitation layer (224) comprised of a metal selected from the group consisting of tantalum, tungsten, and molybdenum onto said second passivation layer (223); applying an ink barrier layer (230) comprised of plastic onto said cavitation layer (224); and securing a plate member (240) having at least one opening (242) therethrough onto said ink barrier layer (230), said ink barrier layer (230) having a section thereof removed directly beneath said opening (242) through said plate member (240) in order to form an ink receiving cavity (250) thereunder, said heating resistor (209) being positioned beneath and in alignment with said ink receiving cavity (250) in order to impart heat thereto.

Claim 7

A method for manufacturing a thermal inkjet printing apparatus comprising the steps of: providing a substrate (70) comprised of silicon; forming a layer (72) of silicon dioxide on said substrate (70); forming a layer (76) of silicon nitride on said layer (72) of silicon nitride; removing a portion of said layer (76) of silicon nitride so as to leave a section (79) of silicon nitride remaining intact on said layer (72) of silicon dioxide, said section (79) of silicon nitride being surrounded by a plurality of exposed regions (80, 82) of said layer (72) of silicon dioxide; oxidizing said substrate (70) beneath said exposed regions (80, 82) of said layer (72) of silicon dioxide in order to form a field oxide layer (84, 86) surrounding said section (79) of silicon nitride; forming a layer (90) of polycrystalline silicon on said section (79) of silicon nitride, said layer (90) of polycrystalline silicon, said section (79) of silicon nitride, and said layer (72) of silicon dioxide thereunder together forming a gate (110) of said transistor (126); forming a transistor source region (118) and a transistor drain region (120) within said substrate (70) adjacent said gate (110); applying a layer (124) of dielectric material onto said field oxide layer (84, 86), said gate (110), said source region (118), and said drain region (120); forming a plurality of openings (174, 176, 177) through said layer (124) of dielectric material in order to provide access to said gate (110), said source region (118), and said drain region (120); applying a layer (180) of electrically resistive material onto said layer (124) of dielectric material, said layer (180) of electrically resistive material being in direct electrical contact with said gate (110), said source region (118), and said drain region (120) through said openings (174, 176, 177); applying a layer (181) of conductive material onto said layer (180) of electrically resistive material in order to form a multi-layer structure (182), said layer (181) of electrically resistive material in said multi-layer structure (182) having at least one uncovered section (202) wherein said layer (181) of conductive material is absent therefrom, said uncovered section (202) functioning as a heating resistor (209), said layer (180) of electrically resistive material being covered with said layer (181) of conductive material at said source region (118), said drain region (120), and said gate (110) of said transistor (126); applying a portion (220) of protective material onto said resistor (209); securing a plate member (240) having at least one opening (242) therethrough onto said portion (220) of protective material, said portion (220) of protective material having a section thereof removed directly beneath said opening (242) through said plate member (240) in order to form an ink receiving cavity (250) thereunder, said heating resistor (209) being positioned beneath and in alignment with said ink receiving cavity (250) in order to impart heat thereto; providing a housing (25, 49) having storage means (22, 44) therein for retaining a supply of liquid ink, said housing (25, 49) further comprising at least one outlet (26, 50) therethrough; and securing said substrate (70) to said housing (25, 49) at a position thereon so that said ink receiving cavity (250) is in fluid communication with said storage means (22, 44) through said outlet (26, 50).

Claim 8

A method for manufacturing a thermal inkjet printing apparatus comprising the steps of: providing a substrate (70) comprised of silicon; forming a layer (72) of silicon dioxide on said substrate (70); forming a layer (76) of silicon nitride on said layer (72) of silicon nitride; removing a portion of said layer (76) of silicon nitride so as to leave a section (79) of silicon nitride remaining intact on said layer (72) of silicon dioxide, said section (79) of silicon nitride being surrounded by a plurality of exposed regions (80, 82) of said layer (72) of silicon dioxide; oxidizing said substrate (70) beneath said exposed regions (80, 82) of said layer (72) of silicon dioxide in order to form a field oxide layer (84, 86) surrounding said section (79) of silicon nitride; forming a layer (90) of polycrystalline silicon on said section (79) of silicon nitride, said layer (90) of polycrystalline silicon comprising an upper surface (96) and a lower surface (94), said lower surface (94) being positioned adjacent said section (79) of silicon nitride, said forming of said layer (90) of polycrystalline silicon further comprising the step of etching said polycrystalline silicon so that said layer (90) of polycrystalline silicon continuously decreases in width from said lower surface (94) to said upper surface (96) thereof, said layer (90) of polycrystalline silicon, said section (79) of silicon nitride, and said layer (72) of silicon dioxide thereunder together forming a gate (110) in said transistor (126); forming a transistor source region (118) and a transistor drain region (120) within said substrate (70) adjacent said gate (110); applying a layer (124) of dielectric material onto said field oxide layer (84, 86), said gate (110), said source region (118), and said drain region (120); forming a plurality of openings (174, 176, 177) through said layer (124) of dielectric material in order to provide access to said gate (110), said source region (118), and said drain region (120); applying a layer (180) of electrically resistive material onto said layer (124) of dielectric material, said layer (180) of electrically resistive material being in direct electrical contact with said gate (110), said source region (118), and said drain region (120) through said openings (174, 176, 177) said layer (180) of electrically resistive material being comprised of a composition selected from the group consisting of polycrystalline silicon, and a mixture of tantalum and aluminum; applying a layer (181) of conductive material onto said layer (180) of electrically resistive material in order to form a multi-layer structure (182), said layer (180) of electrically resistive material in said multi-layer structure (182) having at least one uncovered section (202) wherein said layer (181) of conductive material is absent therefrom, said uncovered section (202) functioning as a heating resistor (209), said layer (180) of electrically resistive material being covered with said layer (181) of conductive material at said source region (118), said drain region (120), and said gate (110) of said transistor (126), said layer (181) of conductive material being comprised of a composition selected from the group consisting of alumina, copper, and gold; applying a first passivation layer (222) comprised of silicon nitride onto said resistor (209); applying a second passivation layer (223) comprised of silicon carbide onto said first passivation layer (222); applying a cavitation layer (224) comprised of a metal selected from the group consisting of tantalum, tungsten, and molybdenum onto said second passivation layer (223); applying an ink barrier layer (230) comprised of plastic onto said cavitation layer (224); and    securing a plate member (240) having at least one opening (242) therethrough onto said ink barrier layer (230), said ink barrier layer (230) having a section thereof removed directly beneath said opening (242) through said plate member (240) in order to form an ink receiving cavity (250) thereunder, said heating resistor (209) being positioned beneath and in alignment with said ink receiving cavity (250) in order to impart heat thereto; providing a housing (25, 49) having storage means (22, 44) therein for retaining a supply of liquid ink, said housing (25, 49) further comprising at least one outlet (26, 50) therethrough; and securing said substrate (70) to said housing (25, 49) at a position thereon so that said ink receiving cavity (250) is in fluid communication with said storage means (22, 44) through said outlet (26, 50).

Claim 9

The apparatus of claims 1, 3, 5, or 7 wherein said layer (90) of polycrystalline silicon of said gate (110) comprises an upper surface (96) and a lower surface (94), said layer (90) of polycrystalline silicon continuously decreasing in width from said lower surface (94) to said upper surface (96) thereof.

Claim 10

The apparatus of claims 1, 2, 3, 4, 5, 6, 7, or 8 wherein said source region (118) and said drain region (120) of said transistor (126) each have a thickness of about 1.25 - 1.75 microns.