Patent EP0520788A2 successfully refreshed from Google Patents.
EP0520788A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Semiconductor memory devices
Assignee: Fujitsu Ltd
•
Filing: 1992-06-25
•
Granted: —
•
Expires: 2012-06-25
Abstract
Abstract A semiconductor memory device, that has a plurality of writing ports (WP₀, WP₁) and reading ports (RP₀ to RP₃) comprises a first data latch portion (11; 111; 211), at least one second data latch portion (12 to 1k; 12 to 14; 112 to 11k; 212, 213), and communication units (41 to 4k, 5; 41 to 44, 51 to 54, 221, 222a, 222b, 223). The first data latch portion (11; 111; 211) is directly accessible by externally entering an address signal, and the second data latch portions (12 to 1k; 12 to 14; 112 to 11k; 212, 213) are connected in parallel to the first data latch portion (11; 111; 211). The communication units (41 to 4k, 5; 41 to 44, 51 to 54, 221, 222a, 222b, 223) is used to access one of the first and second data latch portions (11 to 1k; 11 to 14; 111 to 11k; 211 to 213). Such a semiconductor memory device is applicable to a register file of a microprocessor, for example, and involves a reduced amount of hardware in the register file, particularly in the case of a processor employing parallel processing and local register architecture.
Inventors
- 👤 Akira c/o Fujitsu Limited Katsuno
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-08 03:46
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C8/00; G11C8/16
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
147 words
A semiconductor memory device comprising a plurality of writing ports (WP₀, WP₁) and a plurality of reading ports (RP₀, RP₃), characterised by a plurality of coupled data latches (11 to 1k, 112 to 11k, 211 to 213), each of the writing ports (WP₀, WP₁) being coupled to at least a first of the plurality of latches by a writing control device (21 to 2m, 121 to 12m) and each of the reading ports (RP₀ to RP₃) being coupled to at least the first of the plurality of latches by a reading control device (31 to 3n, 131 to 13n), at least one of said control devices being common to said plurality of latches and there being selection means (41 to 4k, 5, 51 to 54, 221, 222a, 222b, 223) for selecting that one of the latches to be accessed by the common reading and/or writing control device.
Claim 2
Dependent Claim
31 words
A semiconductor memory device according to claim 1, wherein said plurality of coupled data latches (11 to 1k, 112 to 11, 211 to 213) are coupled in parallel with each other.
Claim 3
Dependent Claim
79 words
A semiconductor memory device according claim 1, wherein said writing ports (WP₀, WP₁) and reading ports (RP₀, RP₃) are connected to a first of the data latches (11, 111, 211) by respective ones of the writing and reading control devices, and wherein the or each other latch (12 to 1k, 12 o 14, 112 to 11k, 212, 213) of the plurality of latches is accessed by the common reading and/or writing control device by shifting data through the latches.
Claim 4
Dependent Claim
136 words
A semiconductor memory device having a plurality of writing ports (WP₀, WP₁) and reading ports (RP₀ to RP₃) for carrying out parallel writing and reading operations through said writing ports (WP₀, WP₁) and said reading ports (RP₀ to RP₃), characterized in that said semiconductor memory device comprises: a first data latch portion (11; 111; 211) directly accessible by externally entering an address signal (AD0 to ADj); at least one second data latch portions (12 to 1k; 12 to 14; 112 to 11k; 212, 213) parallel connecting to said first data latch portion (11; 111; 211); and a communication means (41 to 4k, 5; 41 to 44, 51 to 54; 221, 222a, 222b, 223) for accessing one of said first and second data latch portions (11 to 1k; 11 to 14; 111 to 11k; 211 to 213).
Claim 5
Dependent Claim
77 words
A semiconductor memory device as claimed in claim 4, wherein said writing ports (WP₀, WP₁) are operatively connected to said first and second data latch portions (11 to 1k; 11 to 14) through writing control transfer gates (21 to 2m; 21, 22), and said reading ports (RP₀ to RP₃) are operatively connected to said first and second data latch portions (11 to 1k; 11 to 14) through reading control transfer gates (31 to 3n; 31 to 14).
Claim 6
Dependent Claim
87 words
A semiconductor memory device as claimed in claims 4 or 5, wherein said communication means comprises a plurality of data latch portion selecting transfer gates (41 to 44; 41 to 4k: 51 to 54) provided at a respective writing side and reading side relative to said first and second data latch portions (11 to 1k; 11 to 14) parallel connected, for selecting one of said first and second data latch portions (11 to 1k; 11 to 14) in accordance with a selection signal (SS; SS₁ to SS₄).
Claim 7
Dependent Claim
26 words
A semiconductor memory device as claimed in claim 6, wherein said selection signal (SS; SS₁ to S₄) is dependently generated by using a selection register (100).
Claim 8
Dependent Claim
38 words
A semiconductor memory device as claimed in claim 7, wherein said selection signal (SS; SS₁ to SS₄) is generated by using a selection signal decoder (400) receiving a part (AD0, AD1) of said address signal (AD0 to ADj).
Claim 9
Dependent Claim
88 words
A semiconductor memory device as claimed in any one of the preceding claims, wherein writing data are transferred from said writing ports (WP₀, WP₁) to one of said first and second data latch portions (11 to 1k; 11 to 14) through a plurality of bit lines (BL₀, BL₁) for writing, and reading data are transferred from one of said first and second data latch portions (11 to 1k; 11 to 14) to reading ports (RP₀ to RP₃) through a plurality of bit lines (BL₂ to BL₅) for reading.
Claim 10
Dependent Claim
91 words
A semiconductor memory device as claimed in claim 9, wherein the connection between said bit lines (BL₀, BL₁) for writing and said first and second data latch portions (11 to 1k; 11 to 14) are controlled by a plurality of writing port selection gates (21, 22; 21 to 2m), and the connection between said first and second data latch portions (11 to 1k; 11 to 14) and said bit lines (BL₂ to BL₅) for reading are controlled by a plurality of reading port selection gates (31 to 34; 31 to 3n).
Claim 11
Dependent Claim
60 words
A semiconductor memory device as claimed in claim 4, wherein said writing ports (WP₀, WP₁) are operatively connected to said first data latch portion (111; 211) through writing control transfer gates (121 to 12m), and said reading ports (RP₀ to RP₃) are operatively connected to said first data latch portion (111; 211) through reading control transfer gates (131 to 13n).
Claim 12
Dependent Claim
65 words
A semiconductor memory device as claimed in claim 11,wherein said communication means comprises a plurality of shifting control transfer gates (221, 222a, 222B, 223) for shifting data of one of said second data latch portions (212, 213) to said first data latch portion (211) and for accessing one of said first and second data latch portions (211 to 213) in accordance with a control signal.
Claim 13
Dependent Claim
20 words
A semiconductor memory device as claimed in claim 12, wherein said control signal is an externally supplied clock signal (CLK).
Claim 14
Dependent Claim
92 words
A semiconductor memory device as claimed in claim 11, wherein writing data are written from said writing ports (WP₀, WP₁) into said first data latch portion (111; 211) through a plurality of bit lines (BL₀, BL₁) for writing, reading data are read out from said first latch portion (111; 211) to reading ports (RP₀ to RP₃) through a plurality of bit lines (BL₂ to BL₅) for reading, and the data stored in said first data latch portion (111; 211) are shifted to said second data latch portions (112 to 11k; 212, 213).
Claim 15
Dependent Claim
74 words
A semiconductor memory device as claimed in claim 14, wherein the connection between said bit lines (BL₀, BL₁) for writing and said first data latch portions (111; 211) are controlled by a plurality of writing port selection gates (121 to 12m), and the connection between said first data latch portions (111; 211) and said bit lines (BL₂ to BL₅) for reading are controlled by a plurality of reading port selection gates (131 to 13n).
Claim 16
Dependent Claim
83 words
A semiconductor memory device as claimed in any one of the preceding claims, wherein said semiconductor memory device is applied to an arithmetic processing device as a register file (1), and said arithmetic processing device is formed by one chip configuration and has an instruction fetching unit (102) for fetching an instruction, an instruction decoding unit (101) for decoding said instruction fetched in said instruction fetching unit (102), a plurality of arithmetic operation executing units (2, 3) for carrying out parallel arithmetic operations.
Claim 17
Dependent Claim
25 words
A microprocessor having an arithmetic logic unit and, coupled thereto, a register with a semiconductor memory device according to any one of the preceding claims.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.