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EP0518339A2
Expired / Lapsed
EP
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Microcomputer resume function for enhanced microprocessor operating modes and a method for traversing such modes
Assignee: Toshiba Corp
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Filing: 1992-06-11
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Granted: —
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Expires: 2012-06-11
Abstract
Abstract In accordance with the present invention, a resume processing driver for an advanced microprocessor, such as the Intel 80386 operating in enhanced mode, is provided which saves data indicative of the operating conditions of the advanced microprocessor into system memory and then calls a previously existing resume processing routine designed for a previously existing operating system, such as MS-DOS operating in real mode. The previously existing resume processing routine performs additional processing in order to save operating condition data associated with the previously existing operating system into system memory, and then performs a controlled power off sequence and removes the power supplied to all elements of the computer except the computer memory. Thereafter, the existing resume processing routine performs processing to restore the operating condition data associated with the previously existing operating system from system memory and then passes control to the resume processing driver of the present invention. The resume processing driver restores the data indicative of the operating conditions of the advanced microprocessor from system memory, and control then passes to the computer program which was executing before the resume processing driver was initiated. In addition, in another embodiment, the present invention is able to properly switch from the enhanced mode to the real mode and then back to the enhanced mode for use in applications other than resume functions.
Inventors
- 👤 James T.L. c/o Intellectual Property Div. Kou
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-02 19:35
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/46; G06F9/461; G06F9/463
Claims Analysis
Total Claims: 47
Claim 1
Independent Claim
145 words
In a computer system having a central processing unit (CPU) operable in a first and second operational mode, said CPU being able to execute a plurality of instructions and wherein said first and second operational modes utilize different memory addressing and data register schemes, a method of switching from said first operational mode to said second operational mode, and subsequently switching back to said first operational mode, said mode switching method comprising the steps of: (a) saving an operational state of said first operational mode (122), (b) switching from said first operational mode to said second operational mode (124, 125), (c) executing a computer program designed to operate in said second operational mode (Fig. 3e), (d) switching from said second operational mode to said first operational mode (141, 146), and (e) restoring said operational state of said first operational mode saved in step (a) (142).
Claim 2
Dependent Claim
120 words
The mode switching method of claim 1, characterized in that step (a) comprises the steps of: (i) disabling interrupts associated with said CPU (121), (ii) saving a task state register and a machine status register, said registers being associated with said first operational mode of said CPU (122), (iii) saving a global descriptor table register, a local descriptor table register, and an interrupt descriptor table register, said descriptor tables being associated with said first operational mode of said CPU (122), (iv) saving registers associated with a stack, said stack being associated with said first operational mode of said CPU (122), (v) saving processor control registers, said processor control registers being associated with said first operational mode of said CPU (122).
Claim 3
Dependent Claim
71 words
The mode switching method of claim 1, characterized in that step (b) comprises the steps of: (i) switching from said first operational mode to an intermediate operational mode, said intermediate operational mode having an alignment differing from said first operational mode (123), (ii) aligning said plurality of instructions executing on said CPU responsive to step (i) (124), and (iii) switching from said intermediate operational mode to said second operational mode (125).
Claim 4
Dependent Claim
24 words
The mode switching method of claim 3, characterized in that said intermediate operational mode corresponds to an Intel 80286 protected mode of said CPU.
Claim 5
Dependent Claim
21 words
The mode switching method of claim 1, characterized in that said computer program in step (c) is a resume processing program.
Claim 6
Dependent Claim
80 words
The mode switching method of claim 1, characterized in that step (d) comprises the steps of: (i) disabling said interrupts associated with said CPU (140), (ii) switching from said second operational mode to an intermediate operational mode, said intermediate operational mode having an alignment differing from said first operational mode (140), (iii) switching from said intermediate operational mode to said first operational mode (141), and (iv) aligning said plurality of instructions executing on said CPU responsive to step (iii) (141).
Claim 7
Dependent Claim
24 words
The mode switching method of claim 6, characterized in that said intermediate operational mode corresponds to an Intel 80286 protected mode of said CPU.
Claim 8
Dependent Claim
143 words
The mode switching method of claim 1, characterized in that step (e) comprises the steps of: (i) restoring a task state register and a machine status register, said registers being associated with said first operational mode of said CPU and being previously saved in step (a) (142), (ii) restoring a global descriptor table register, a local descriptor table register, and an interrupt descriptor table register, said descriptor tables being associated with said first operational mode of said CPU and being previously saved in step (a) (142), (iii) restoring registers associated with a stack, said stack being associated with said first operational mode of said CPU and said registers being previously saved in step (a) (142), and (iv) restoring processor control registers, said processor control registers being associated with said first operational mode of said CPU and being previously saved in step (a) (142).
Claim 9
Dependent Claim
17 words
The mode switching method of claim 1, characterized in that said CPU is an Intel 80386-compatible microprocessor.
Claim 10
Dependent Claim
22 words
The mode switching method of claim 9, characterized in that said first operational mode corresponds to an enhanced mode of said CPU.
Claim 11
Dependent Claim
21 words
The mode switching method of claim 9, characterized in said second operational mode corresponds to a real mode of said CPU.
Claim 12
Dependent Claim
23 words
The mode switching method of claim 10, characterized in that said first operational mode corresponds to an 80386 protected mode of said CPU.
Claim 13
Dependent Claim
23 words
The mode switching method of claim 10, characterized in that said first operational mode corresponds to a virtual 8086 mode of said CPU.
Claim 14
Dependent Claim
90 words
The mode switching method of claim 13, characterized in that step (b) comprises the steps of: (i) switching from said first operational mode to a first intermediate operational mode (120), (ii) switching from said first intermediate operational mode to a second intermediate operational mode, said second intermediate operational mode having an alignment differing from said first intermediate operational mode (124), (iii) aligning said plurality of instructions executing on said CPU responsive to step (ii) (124), and (iv) switching from said second intermediate operational mode to said second operational mode (125).
Claim 15
Dependent Claim
24 words
The mode switching method of claim 14, characterized in that said first intermediate operational mode corresponds to an 80386 protected mode of said CPU.
Claim 16
Dependent Claim
24 words
The mode switching method of claim 14, characterized in that said second intermediate operational mode corresponds to an 80286 protected mode of said CPU.
Claim 17
Dependent Claim
99 words
The mode switching method of claim 13, characterized in that step (d) comprises the steps of: (i) disabling said interrupts associated with said CPU (140), (ii) switching from said second operational mode to a second intermediate operational mode, said second intermediate operational mode having an alignment differing from a first intermediate operational mode (141), (iii) switching from said second intermediate operational mode to said first intermediate operational mode (142), (iv) switching from said first intermediate operational mode to said first operational mode (146), and (v) aligning said plurality of instructions executing on said CPU responsive to step (iii) (146).
Claim 18
Dependent Claim
24 words
The mode switching method of claim 17, characterized in that said first intermediate operational mode corresponds to an 80386 protected mode of said CPU.
Claim 19
Dependent Claim
24 words
The mode switching method of claim 17, characterized in that said second intermediate operational mode corresponds to an 80286 protected mode of said CPU.
Claim 20
Dependent Claim
24 words
The mode switching method of claim 1, characterized in that steps (a)-(d) are performed responsive to a power-off request being detected by said CPU.
Claim 21
Dependent Claim
24 words
The mode switching method of claim 1, characterized in that steps (a)-(d) are performed responsive to a non-maskable interrupt being detected by said CPU.
Claim 22
Dependent Claim
25 words
The mode switching method of claim 1, characterized in that steps (a)-(d) are performed responsive to a low battery condition being detected by said CPU.
Claim 23
Dependent Claim
156 words
In a computer system having a central processing unit (CPU) operable in a first and second operational mode, said CPU being able to execute a plurality of instructions and wherein said first and second operational modes utilize different memory addressing and data register schemes, a method of saving and subsequently restoring system data indicative of the CPU's operating conditions in response to a power-off signal and a subsequent power-on signal, said method comprising the steps of: (a) initializing a resume processing driver to perform the following steps (101-113), (b) saving an operational state of said first operational mode (122), (c) switching from said first operational mode to said second operational mode, (d) executing a computer program designed to operate in said second operational mode (Fig. 2e), (e) switching from said second operational mode to said first operational mode (141, 146), and (f) restoring said operational state of said first operational mode saved in step (b) (142).
Claim 24
Dependent Claim
99 words
The method of claim 23, characterized in that step (a) comprises the steps of: (i) allocating a block of memory located below a 1 MByte boundary associated with said CPU for use by switching steps (c) and (e) (107), (ii) hooking an NMI handler vector so that step (iv), below, is performed when an NMI is detected by said CPU (111), (iii) copying a routine associated with steps (c) and (e) to said block of memory (112), and (iv) hooking a resume event processing routine so that steps (b)-(f) are performed responsive to said resume event being requested (113).
Claim 25
Dependent Claim
119 words
The method of claim 23, characterized in that step (b) comprises the steps of: (i) disabling interrupts associated with said CPU (121), (ii) saving a task state register and a machine status register, said registers being associated with said first operational mode of said CPU (122), (iii) saving a global descriptor table register, a local descriptor table register, and an interrupt descriptor table register, said descriptor tables being associated with said first operational mode of said CPU (122), (iv) saving registers associated with a stack, said stack being associated with said first operational mode of said CPU (122), and (v) saving process control registers, said processor control registers being associated with said first operational mode of said CPU (122).
Claim 26
Dependent Claim
69 words
The method of claim 23, characterized in that step (c) comprises the steps of: (i) switching from said first operational mode to an intermediate operational mode, said intermediate operational mode having an alignment differing from said first operational mode (124), (ii) aligning said plurality of instructions executing on said CPU responsive to step (i) (124), and (iii) switching from said intermediate operational mode to said second operational mode (125).
Claim 27
Dependent Claim
22 words
The method of claim 26, characterized in that said intermediate operational mode corresponds to an Intel 80286 protected mode of said CPU.
Claim 28
Dependent Claim
30 words
The method of claim 23, characterized in that said computer program in step (d) is a resume processing program residing within a Basic Input/Output System (BIOS) of said computer system.
Claim 29
Dependent Claim
78 words
The method of claim 23, characterized in that step (e) comprises the steps of: (i) disabling said interrupts associated with said CPU (140), (ii) switching from said second operational mode to an intermediate operational mode, said intermediate operational mode having an alignment differing from said first operational mode (141), (iii) switching from said intermediate operational mode to said first operational mode (142), and (iv) aligning said plurality of instructions executing on said CPU responsive to step (iii) (143).
Claim 30
Dependent Claim
22 words
The method of claim 29, characterized in that said intermediate operational mode corresponds to an Intel 80286 protected mode of said CPU.
Claim 31
Dependent Claim
145 words
The method of claim 23, characterized in that step (f) comprises the steps of: (i) restoring a task state register and a machine status register, said registers being associated with said first operational mode of said CPU and being previously saved in step (b) (142, 143), (ii) restoring a global descriptor table register, a local descriptor table register, and an interrupt descriptor table register, said descriptor tables being associated with said first operational mode of said CPU and being previously saved in step (b) (142, 143), (iii) restoring registers associated with a stack, said stack being associated with said first operational mode of said CPU and said registers being previously saved in step (b) (142, 143), and (iv) restoring processor control registers, said processor control registers being associated with said first operational mode of said CPU and being previously saved in step (b) (142, 143).
Claim 32
Dependent Claim
17 words
The mode switching method of claim 23, characterized in that said CPU is an Intel 80386-compatible microprocessor.
Claim 33
Dependent Claim
22 words
The mode switching method of claim 32, characterized in that said first operational mode corresponds to an enhanced mode of said CPU.
Claim 34
Dependent Claim
22 words
The mode switching method of claim 32, characterized in that said second operational mode corresponds to a real mode of said CPU.
Claim 35
Dependent Claim
23 words
The mode switching method of claim 33, characterized in that said first operational mode corresponds to an 80386 protected mode of said CPU.
Claim 36
Dependent Claim
23 words
The mode switching method of claim 33, characterized in that said first operational mode corresponds to a virtual 8086 mode of said CPU.
Claim 37
Dependent Claim
91 words
The mode switching method of claim 36, characterized in that step (c) comprises the steps of: (i) switching from said first operational mode to a first intermediate operational mode (120), (ii) switching from said first intermediate operational mode to a second intermediate operational mode, said second intermediate operational mode having an alignment differing from said first intermediate operational mode (123, 124), (iii) aligning said plurality of instructions executing on said CPU responsive to step (ii) (124), and (iv) switching from said second intermediate operational mode to said second operational mode (125).
Claim 38
Dependent Claim
24 words
The mode switching method of claim 37, characterized in that said first intermediate operational mode corresponds to an 80386 protected mode of said CPU.
Claim 39
Dependent Claim
24 words
The mode switching method of claim 37, characterized in that said second intermediate operational mode corresponds to an 80286 protected mode of said CPU.
Claim 40
Dependent Claim
99 words
The mode switching method of claim 36, characterized in that step (e) comprises the steps of: (i) disabling said interrupts associated with said CPU (140), (ii) switching from said second operational mode to a second intermediate operational mode, said second intermediate operational mode having an alignment differing from a first intermediate operational mode (141), (iii) switching from said second intermediate operational mode to said first intermediate operational mode (142), (iv) switching from said first intermediate operational mode to said first operational mode (146), and (v) aligning said plurality of instructions executing on said CPU responsive to step (iii) (146).
Claim 41
Dependent Claim
24 words
The mode switching method of claim 40, characterized in that said first intermediate operational mode corresponds to an 80386 protected mode of said CPU.
Claim 42
Dependent Claim
24 words
The mode switching method of claim 40, characterized in that said second intermediate operational mode corresponds to an 80286 protected mode of said CPU.
Claim 43
Dependent Claim
24 words
The mode switching method of claim 23, characterized in that steps (a)-(d) are performed responsive to a power-off request being detected by said CPU.
Claim 44
Dependent Claim
24 words
The mode switching method of claim 23, characterized in that steps (a)-(d) are performed responsive to a non-maskable interrupt being detected by said CPU.
Claim 45
Dependent Claim
25 words
The mode switching method of claim 23, characterized in that steps (a)-(d) are performed responsive to a low battery condition being detected by said CPU.
Claim 46
Dependent Claim
17 words
The method of claim 23, characterized in that said CPU is operating under the Microsoft Windows environment.
Claim 47
Dependent Claim
18 words
The method of claim 23, characterized in that said resume processing driver is a Microsoft Windows device driver.
References Cited (Backward Citations)
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