Method of forming a multilayer wiring structure on a semiconductor device

Claim 1

A method for manufacturing a semiconductor device, comprising the step of forming an interlayer insulator layer on a semiconductor substrate; forming a power supply layer for electroplating on an upper surface of said intedayer insulator layer; depositing on said power supply layer a patterned photoresist layer having at least one groove for formation of at least one wiring conductor; depositing a metal layer on said power supply layer by an electroplating process using said patterned photoresist layer as a mask so that the wiring conductor is formed within the or each of said grooves; removing said photoresist layer depositing an insulator film on a surface including a surface of said at least one wiring-conductor; etching back the deposited insulator film so that the deposited insulator film remains on only side surfaces of said at least one wiring conductor and the upper surface of said power supply layer is exposed; etch-removing said power supply layer using said at least one wiring conductor and said remaining deposited insulator film as a mask; and etch-removing said remaining deposited insulator film.

Claim 2

A method for manufacturing a semiconductor device, comprising the step of forming an interlayer insulator layer on a semiconductor substrate; forming a power supply layer for electroplating on an upper surface of said intedayer insulator layer; depositing on said power supply layer a patterned photoresist layer having at least one groove for formation of at least one wiring conductor; depositing a metal layer on said power supply layer by an electroplating process using said patterned photoresist layer as a mask so that the wiring conductor is formed within the or each of said grooves; removing said photoresist layer depositing an insulator film on a surface including a surface of said at least one wiring-conductor; etching back the deposited insulator film so that the deposited insulator film remains on only side surfaces of said at least one wiring conductor and the upper surface of said power supply layer is exposed; etch-removing said power supply layer using said at least one wiring conductor and said remaining deposited insulator film as a mask; and etch-removing said remaining deposited insulator film.

Claim 5

A method claimed in any preceding claim wherein said power supply layer is formed of a barrier metal layer deposited on said interlayer insulator film and a gold layer deposited on said barrier metal layer, and wherein said power supply layer is removed by removing said gold layer and said barrier metal layer in the named order by a sputter etching using an inert gas such as Ar, using said wiring conductors and the remaining deposited insulator film as a mask.

Claim 6

A method claimed in any preceding claim wherein said insulator film is formed of a silicon oxide film, and said etch-removal of said remaining deposited insulator film formed of the silicon oxide film is performed by a dilute hydrofluoric acid.

Claim 7

A method claimed in any of Claims 1 to 4 wherein said insulator film is formed of a silicon nitride film, and said etch-removal of said remaining deposited insulator film formed of the silicon nitride film is performed by an isotropic dry etching.

Claim 8

A method claimed in any of Claims 1 to 3 wherein said power supply layer is formed of a barrier metal layer deposited on said interlayer insulator film and a gold layer deposited on said barrier metal layer, and wherein after said power supply layer is removed using said wiring conductors and the remaining deposited insulator film as a mask, said gold layer is wet-etched by aqua regia, and said barrier metal layer is wet-etched by H 2 0 2 solution, so that a most portion of the metal deposit which might be adhered to the remaining deposited insulatorfilm is etch-removed, and thereafter, the remaining deposited insulatorfilm is removed by a wet etching.

Claim 9

A method for manufacturing a semiconductor device, comprising the step of forming on a semiconductor substrate an interlayer insulator layer having a planarized upper surface; selectively forming in said interlayer insulator layer a contact hole in alignment with a lower level wiring conductor formed under said interlayer insulator layer; forming a power supply layer for electroplating on said upper surface of said interlayer insulator layer including a surface of said contact hole; depositing a photoresist layer on said power supply layer; patterning said deposited photoresist layer so as to form a groove for formation of an upper level wiring conductor, said groove being in alignment with said contact hole; depositing a metal layer on said power supply layer by an electroplating process using said photoresist layer as a mask so that said second level wiring conductor is formed within said groove; removing said photoresist layer, depositing an insulatorfilm on a surface including a surface of said second level wiring conductor; etching back the deposited insulator film so that the deposited insulator film remains on only side surfaces of said second level wiring conductor and the upper surface of said power supply layer is exposed; etch-removing said power supply layer using said second level wiring conductor and said remaining deposited insulator film as a mask: and etch-removing said remaining deposited insulator film.

Claim 10

A method for manufacturing a semiconductor device, comprising the step of forming on a semiconductor substrate an interlayer insulator layer having a planarized upper surface; selectively forming in said interlayer insulator layer a contact hole in alignment with a lower level wiring conductor formed under said interlayer insulator layer; forming a power supply layer for electroplating on said upper surface of said interlayer insulator layer including a surface of said contact hole; depositing a photoresist layer on said power supply layer; patterning said deposited photoresist layer so as to form a groove for formation of an upper level wiring conductor, said groove being in alignment with said contact hole; depositing a metal layer on said power supply layer by an electroplating process using said photoresist layer as a mask so that said second level wiring conductor is formed within said groove; removing said photoresist layer, depositing an insulatorfilm on a surface including a surface of said second level wiring conductor; etching back the deposited insulator film so that the deposited insulator film remains on only side surfaces of said second level wiring conductor and the upper surface of said power supply layer is exposed; etch-removing said power supply layer using said second level wiring conductor and said remaining deposited insulator film as a mask: and etch-removing said remaining deposited insulator film.

Claim 11

A method for manufacturing a semiconductor device having a multi-layer wiring structure, including the steps of forming a power supply layer for electroplating on an interlayer insulator layer, forming a patterned second level wiring conductor on said power supply layer, depositing an insulator film on the surface of said second level wiring conductor, etching back said insulator film so that said insulator film remains only on the side surfaces of said second level wiring conductor, removing said power supply layer by etching using said remaining insulator film and said second level wiring conductor as a mask, and etch-removing said remaining insulator film.

Claim 12

A method for manufacturing a semiconductor device having a multi-layer wiring structure, including the steps of forming a power supply layer for electroplating on an interlayer insulator layer, forming a patterned second level wiring conductor on said power supply layer, depositing an insulator film on the surface of said second level wiring conductor, etching back said insulator film so that said insulator film remains only on the side surfaces of said second level wiring conductor, removing said power supply layer by etching using said remaining insulator film and said second level wiring conductor as a mask, and etch-removing said remaining insulator film.