Adaptive maximum likelihood sequence estimator using channel estimators of respective order of impulse response

Claim 2

An adaptive maximum likelihood sequence estimator as claimed in claim 1, wherein said second summing means comprises: a plurality of first, raise-to-power multipliers of zero-th to m-th order coupled to said time base for raising the time-count value to powers of respective order to produce a plurality of power-raised time-count values; a plurality of second multipliers for multiplying the second signals from said (m + 1) channel estimators with the outputs of said first multipliers, respectively; and an adder for summing the outputs of said second multipliers to produce said fourth signal, wherein said reset means comprises; means, responsive to said reset signal, for initializing said fourth signal from said adder and causing the zero-th order channel estimator to reset to the initialized fourth signal, and for initializing the second signals from the first-order to the m-th order channel estimators and causing the last-mentioned estimators to reset to the initialized second signals.

Claim 3

An adaptive maximum likelihood sequence estimator as claimed in claim 1, wherein said second summing means comprises: means for storing data representing a predetermined amount of time; a first adder for summing said data with the time-count value from said time base; a plurality of first, raise-to-poker multipliers of zero-th to m-th order coupled to said first adder for raising the summed count value to powers of respective order to produce a plurality of power-raised time-count values; a plurality of second multipliers for multiplying the second signals from said (m + 1) channel estimators with the outputs of said first multipliers, respectively; a second adder for summing the outputs of said second multipliers to produce said fourth signal; a plurality of third, raise-to-power multipliers of zero-th to m-th order coupled to said time-base for raising the time-count value to powers of respective order to produce a plurality of power-raised time-count values; a plurality of fourth multipliers for multiplying the second signals from said (m + 1) channel estimators with the outputs of said third multipliers; and a third adder for summing the outputs of said fourth multipliers to produce a summed signal, wherein said reset means comprises; means, responsive to said reset signal, for initializing said summed signal from said third adder and causing the zero-th order channel estimator to reset to the initialized summed signal, and for initializing the second signals from the first-order to the m-th order channel estimators and causing the last-mentioned estimators to reset to the initialized second signals.

Claim 4

An adaptive maximum likelihood sequence estimator as claimed in claim 1, wherein each of said channel estimators comprises: a plurality of shift registers (203, 204) connected to form a tapped delay line having a plurality of successive taps along the delay line for receiving said decision sequence from said maximum likelihood sequence estimator; a first, raise-to-power multiplier (217) coupled to said time base for raising the time-count valve to a power corresponding to the order of the channel estimator; a plurality of second multipliers (211, 212, 213) for multiplying the power-raised time-count value with components of said decision sequence respectively appearing at said successive taps; a plurality of registers (205, 206, 207); processor means (210) for receiving signals from said difference detector, said first multipliers and said registers and performing calculations on the received signals to produce a plurality of error-compensated signal components of the second signal of the channel estimator for coupling to said registers; a plurality of third multipliers (214, 215, 216) for multiplying the outputs of said second multipliers with contents of said registers, respectively; and a first adder (208) for summing the outputs of said second multipliers to produce a sum and applying the sum to said first summing means (17) as said first signal, wherein said second summing means comprises: a plurality of fourth, raise-to-power multipliers (302) of zero-th to m-th order coupled to said time base for raising the time-count value to powers of respective order to produce a plurality of power-raised time-count values; a plurality of fifth multipliers (301) for multiplying the second signals from said (m + 1) channel estimators with the outputs of said fourth multipliers, respectively; and a third adder (302) for summing the outputs of said fifth multipliers (301) to produce sad fourth signal, wherein said reset means comprises: means, responsive to said reset signal, for initializing said fourth signal from said third adder (302) and causing the zero-th order channel estimator (20-0) to reset to the initialized fourth signal, and for initializing the second signals from the first-order to the m-th order channel estimators (20-1 ∼ 20-m) and causing the last-mentioned estimators to respectively reset to the initialized second signals.

Claim 5

An adaptive maximum likelihood sequence estimator as claimed in claim 1, wherein each of said channel estimators comprises: a plurality of shift registers (203, 204) connected to form a tapped delay line having a plurality of successive taps along the delay line for receiving said decision sequence from said maximum likelihood sequence estimator; a first, raise-to-power multiplier(217) coupled to said time base for raising the time-count value to a power corresponding to the order of the channel estimator; a plurality of second multipliers (211, 212, 213) for multiplying the power-raised time-count value with components of said decision sequence respectively appearing at said successive taps; a plurality of registers (205, 206, 207); processor means (210) for receiving signals from said difference detector, said first multipliers and said registers and performing calculations on the received signals to produce a plurality of error-compensated signal components of the second signal of the channel estimator for coupling to said registers; a plurality of third multipliers (214, 215, 216) for multiplying the outputs of said second multipliers with contents of said registers, respectively; and an adder (208) for summing the outputs of said second multipliers to produce a sum and applying the sum to said first summing means (17) as said first signal, wherein said reset means comprises: means (303), responsive to said reset signal, for initializing said fourth signal from said second summing means (300, 301, 302) and resetting the registers (205, 206, 207) of the zero-th order channel estimator (20-0) to the initialized fourth signal and resetting the registers of the first- to the m-th channel estimators (20-1 - 20-m) to initial values of the error-compensated signal components of the respective channel estimators, and wherein said second summing means comprises: means (400) for storing data representing a predetermined amount of time; a second adder (401) for summing said data with the time-count value from said time base; a plurality of fourth, raise-to-power multipliers (300) of zero-th to m-th order coupled to said second adder (401) for raising the summed count value to powers of respective order to produce a plurality of power-raised time-count values; a plurality of fifth multipliers (301) for multiplying the second signals from said (m + 1) channel estimators with the outputs of said fourth multipliers (300), respectively; a third adder (302) for summing the outputs of said fifth multipliers (301) to produce said fourth signal; a plurality of sixth, raise-to-power multipliers (402) of zero-th to m-th order coupled to said time-base for raising the time-count value to powers of respective order to produce a plurality of power-raised time-count values; a plurality of seventh multipliers (403) for multiplying the second signals from said (m + 1) channel estimators with the outputs of said sixth multipliers (402); and a fourth adder (404) for summing the outputs of said seventh multipliers (403) to produce a summed signal, wherein said reset means comprises: means, responsive to said reset signal, for initializing said summed signal from said fourth adder (404) and causing the zero-th order channel estimator to reset to the initialized summed signal, and for initializing the second signals from the first order to the m-th order channel estimators and causing the last-mentioned estimators to respectively reset to the initialized second signals.

Claim 6

An adaptive maximum likelihood sequence estimator for receiving a signal transmitted through a communication channel having a time-varying channel impulse response, comprising: a time base for generating a clock pulse and a time-count value of said clock pulse which increases from an initial value to a predetermined value and generating a reset signal at periodic intervals when said time-count value reaches said predetermined value; an analog-to-digital converter for sampling the received signal in response to said clock pulse and converting the sampled signal into a digital signal; a maximum likelihood sequence estimator coupled to the analog-to-digital converter for deriving a decision sequence of the digital signal from an estimate of said channel impulse response; a delay circuit for introducing a delay time to said digital signal by an amount substantially corresponding to the amount of time taken by said maximum likelihood sequence estimator to produce said decision sequence; a difference detector for generating an error signal representative of the difference between the delayed signal and a replica of the transmitted signal; (m + 1) channel estimators provided respectively for zero-th order through m-th order of the channel impulse response, each of the channel estimators operating on said time-count value and being responsive to the output of said difference detector and the decision sequence from said maximum likelihood sequence estimator for deriving therefrom a first signal representing a respective order of said replica and a second signal representing a respective order of said channel impulse response, each of said first and second signals having a value incremental with said time-count value; first summing means for summing the first signals from said channel estimators to produce a third signal and applying the third signal to said difference defector as said replica; second summing means for summing the second signals from said channel estimators to produce a fourth signal and applying the fourth signal to said maximum likelihood sequence estimators as said estimate of the channel Impulse response; and reset means, responsive to said reset signal, for initializing said fourth signal from said second summing means and causing the zero-th order channel estimator to reset to the initialized fourth signal, and for initializing the second signals from the first-order to the m-th order channel estimators and causing the last-mentioned estimators to respectively reset to the initialized second signals.