Patent EP0516042A2 successfully refreshed from Google Patents.
EP0516042A2
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ATM cell error processing system
Assignee: Fujitsu Ltd
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Filing: 1992-05-26
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Granted: —
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Expires: 2012-05-26
Abstract
Abstract An ATM cell error processing system includes a plurality of error detectors (30) for respectively detecting predetermined cell errors and for respectively generating decision signals, an error editing unit (31) which is operatively coupled to the error detector and determines, on the basis of the decision signals, whether or not a cell related to the decision signals should be discarded. A buffer (32), which is coupled to at least one of the error detector, temporarily stores the cell. An error cell discarding unit (33), which is coupled to the error editing unit and the buffer, discards the cell from the buffer when the error editing unit determines that the cell should be discarded and relays the cell when the error editing unit does not determine that the cell should be discarded.
Inventors
- 👤 Ryuichi C/O Fujitsu Limited Takechi
- 👤 Takeshi c/o Fujitsu Limited Kawasaki
- 👤 Jyoei c/o Fujitsu Limited Kamoi
- 👤 Kazuo c/o Fujitsu Limited Hajikano
- 👤 Satoshi C/O Fujitsu Limited Kuroyanagi
- 👤 Toshio c/o Fujitsu Limited Shimoe
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-03 22:52
CPC Classifications
H; H04; H04Q; H04Q11/00; H04Q11/04; H04Q11/0428; H04Q11/0478; H04L; H04L1/00; H04L1/0078; H04L1/0083; H04L12/00; H04L12/54; H04L12/56; H04L12/5601; H04L2012/5638; H04L2012/5646
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
132 words
An ATM cell error processing system comprising: a plurality of error detection means (30) for respectively detecting predetermined cell errors and for respectively generating decision signals; error editing means (31), operatively coupled to said error detection means, for determining, on the basis of the decision signals, whether or not a cell related to the decision signals should be discarded; buffer means (32), coupled to at least one of the error detection means, for temporarily storing said cell; and error cell discarding means (33), coupled to said error editing means and said buffer means, for discarding said cell from said buffer means when said error editing means determines that said cell should be discarded and for relaying said cell when said error editing means does not determine that said cell should be discarded.
Claim 2
Dependent Claim
57 words
An ATM cell error processing system as claimed in claim 1, characterized in that: the plurality of error detection means are connected in series; and one of the plurality of error detection means located at a final stage of a series of the error detection means is coupled to said error editing means and said buffer means.
Claim 3
Dependent Claim
48 words
An ATM cell error processing system as claimed in claim 1, characterized in that: the plurality of error detection means are connected in parallel and coupled to said error editing means; and said cell is simultaneously applied to the plurality of error detection means and said buffer means.
Claim 4
Dependent Claim
42 words
An ATM cell error processing system as claimed in claim 2, characterized in that the plurality of error detection means respectively comprise means (40) for inserting the decision signals into respective, predetermined bit positions of a next cell subsequent to said cell.
Claim 5
Dependent Claim
23 words
An ATM cell error processing system as claimed in claim 4, characterized in that each of said decision signals is a one-bit signal.
Claim 6
Dependent Claim
51 words
An ATM cell error processing system as claimed in claim 1, characterized in that said ATM cell error processing system further comprises transfer means (44, 50) for transferring the decision signals to said error editing means through a signal line different from a signal line through which said cell is transferred.
Claim 7
Dependent Claim
47 words
An ATM cell error processing system as claimed in claim 6, characterized in that: said signal line transfers an error flag signal; and the plurality of cell error detection means respectively comprises means (44) for inserting, as error flags, the decision signals into said error flag signal.
Claim 8
Dependent Claim
25 words
An ATM cell error processing system as claimed in claim 7, characterized in that said error flag signal is synchronized with outputting of said cell.
Claim 9
Dependent Claim
53 words
An ATM cell error processing system as claimed in claim 1, characterized in that said error editing means comprises logic means (63, 70) for executing a predetermined logic operation on said decision signals and for determining whether or not said cell should be discarded based on a result of said predetermined logic operation.
Claim 10
Dependent Claim
41 words
An ATM cell error processing system as claimed in claim 9, characterized in that said predetermined logic operation comprises a logic operation that determines that said cell should be discarded when at least two of said decision signals indicate cell errors.
Claim 11
Dependent Claim
43 words
An ATM cell error processing system as claimed in claim 9, characterized in that said error editing means comprises error register means (61, 62), coupled to said logic means, for temporarily storing said decision signals transferred from the plurality of error detection means.
Claim 12
Dependent Claim
125 words
An ATM cell error processing system as claimed in claim 1, characterized in that said error editing means comprises: error register means (61, 62), coupled to said logic means, for temporarily storing said decision signals transferred from the plurality of error detection means; masking logic means (20, 70), coupled to said error register means, for executing a masking logic operation on said decision signals from said error register means and error masking information, so that necessary decision signals among said decision signals from said error register means are selected by said masking information; and cell discarding logic means (33), coupled to said masking logic means, for executing a cell discarding logic operation on the basis of said necessary decision signals from said masking logic means.
Claim 13
Dependent Claim
33 words
An ATM cell error processing system as claimed in claim 12, characterized in that: said error register means comprises AND gates (71); and said cell discarding logic means comprises an OR gate (72).
Claim 14
Dependent Claim
88 words
An ATM cell error processing system as claimed in claim 2, characterized in that said ATM cell error processing system further comprises: test cell generating means (80) for generating a test cell having, in a predetermined bit position thereof, a bit for identifying the test cell; and selector means (81), coupled to said test cell generating means, for outputting either said cell or the test cell to one of the plurality of error detection means located at a first stage of a series of the error detection means.
Claim 15
Dependent Claim
72 words
An ATM cell error processing system as claimed in claim 3, characterized in that said ATM cell error processing system further comprises: test cell generating means (80) for generating a test cell having, in a predetermined bit position thereof, a bit for identifying the test cell; and selector means (81), coupled to said test cell generating means, for outputting either said cell or test cell to the plurality of error detection means.
References Cited (Backward Citations)
No citation records indexed.
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